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41. 发明专利

JPH01280335A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE OF THE SAME 失效
公开(公告)号：JPH01280335A
公开(公告)日：1989-11-10
申请号：JP10978188
申请日：1988-05-02
申请人： HITACHI LTD
发明人： SUWAUCHI NAOKATSU , TSUCHIYA OSAMU
IPC分类号： H01L23/52 , H01L21/20 , H01L21/28 , H01L21/285 , H01L21/31 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L23/522 , H01L23/532 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/43
摘要： PURPOSE:To reduce the generation of precipitation of silicon inside a wiring to be connected through a silicon film in a semiconductor region and improve an electrical reliability by a method wherein a shielding film for shielding the precipitation of silicon atoms of an insulation film is provided between at least the under surface or the top surface of a wiring of Al alloy film or the like and a silicon-based insulation film. CONSTITUTION:In a semiconductor integrated circuit device where a wiring 18 with an aluminum film or its alloy film as a main body and which its surrounding is coated with silicon-based insulating film 16, 19 connected to a semiconductor region 13 formed on the main surface of a single crystal silicon substrate 1, shield film 18A, 18C for shielding the precipitation of silicon atoms inside insulation films 16, 19 is provided between at least the under surface and the top surface of the above wiring 18 and the insulating films 16, 19. For example, the above shield films 18A, 18C are formed with conductive barrier metals such as MoSi2, TiSi2TiN, WN. The shielding film 18A is also provided on the under surface of the wiring 18 of the connection section between the above silicon film 15 and the wiring 18 so that the shielding film 18A of that portion is used as a barrier metal film.

42. 发明专利

JPH01272147A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01272147A
公开(公告)日：1989-10-31
申请号：JP10031688
申请日：1988-04-25
申请人： HITACHI LTD
发明人： OTSUKA FUMIO , TSUCHIYA OSAMU
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L27/10 , H01L29/78
摘要： PURPOSE:To ensure the breakdown strength of an n-channel MISFET by making an insulating film on the sidewall of a p-channel MISFET smaller than that on the sidewall of the n-channel MISFET in a semiconductor integrated circuit device with a CMOS adopting LDD structure. CONSTITUTION:Length in the channel length direction of a semiconductor region 18 is constituted in size smaller than semiconductor regions 9 in a MISFETQn and a MISFETQS. That is, a sidewall insulating film 19 is organized so that length in the channel length direction is made smaller than a sidewall insulating film 16 in the MISFETQn and a sidewall insulating film 10 in the MISFETQS. The sidewall insulating film 19 is constructed in size smaller than 0.3mum such as 0.1mu-0.25mum on a 1.3mum process. That is, since the series resistance value of a semiconductor region (between a source region and a drain region) 20 can be lowered, current driving force can be increased while a section (between a source region and a drain region) between semiconductor regions 17 can be isolated, thus ensuring breakdown strength between the semiconductor regions 17.

43. 发明专利

JP2001036034A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2001036034A
公开(公告)日：2001-02-09
申请号：JP20467399
申请日：1999-07-19
申请人： HITACHI LTD
发明人： OKAZAKI TSUTOMU , IKEDA YOSHIHIRO , TSUCHIYA OSAMU
IPC分类号： H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase process margins in photolithography and etching techniques for the formation of active regions by placing in a memory region a plurality of active regions having band-like planar shape at regular intervals in the direction of the width. SOLUTION: A semiconductor substrate 1 is oxidized by heating to form a pad insulating film 4 on the major surface of the semiconductor substrate 1. An insulating film 5 is formed thereon, and the pad insulating film 4 and the insulating film 5 are processed using photolithography and etching techniques so as to reduce line/space to minimum processing dimensions. Thus a plurality of the pad insulating films 4 and insulating films 5 extending in planar bandlike pattern are formed on the major surface of the semiconductor substrate 1 at regular intervals in the direction of their width. Therefore, the planar dimensions of patterns can be increased, and further process margins in photolithography and etching processes for patterning the insulating film 5 and the like can be enlarged.

44. 发明专利

JPH11345945A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11345945A
公开(公告)日：1999-12-14
申请号：JP15088898
申请日：1998-06-01
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KUBOTA KATSUHIKO , SUZUKI CHIKASHI , TADAKI YOSHITAKA , OGISHIMA JUNJI , TSUCHIYA OSAMU , ASAKURA HISAO , WATABE KOZO
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To realize a DRAM having the excellent refleshing characteristics without decreasing the threshold voltage of a memory-cell selecting MISFET (metal-insulator semiconductor field-effect transistor). SOLUTION: In a channel region, high-concentration boron for adjusting a threshold voltage is introduced. At the lower part of a pair of n-type semiconductor region constituting a source and a drain, an electric-field alleviating layer constituted of phosphor is formed. Furthermore, at the sloping region of the concentration distribution of the boron for adjusting the threshold voltage, arsenic is introduced. At the region, wherein the arsenic is introduced, the concentration distribution of the above described boron becomes low. The impurity concentration of the semiconductor substrate at the metallurgical bonding position of the electric-field alleviating layer and the semiconductor substrate becomes low to the degree of 1×10 cm .

45. 发明专利

JPH11111868A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11111868A
公开(公告)日：1999-04-23
申请号：JP26969397
申请日：1997-10-02
申请人： HITACHI LTD
发明人： IKEDA YOSHIHIRO , OKAZAKI TSUTOMU , TSUCHIYA OSAMU
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a gate electrode provided with the side wall spacer of high performance, high reliability and its manufacture. SOLUTION: In an AND type FLASH memory or the like, the side wall spacer is provided on the side wall of a gate electrode 6 on a silicon oxide film (gate insulation film) 5. The side wall spacer is provided with a silicon oxide film 9 formed by thermally oxidizing the semiconductor area of the edge of the gate electrode 6 and a well 4 on a semiconductor substrate (substrate) 1 at the lower part of the edge, etc., a silicon oxide film 10 formed on the side wall of the silicon oxide film 9 by using a CVD method, a silicon nitride film 14 formed on the side wall of the silicon oxide film 10, and a silicon oxide film 15 formed on the side wall of the silicon nitride film 14.

46. 发明专利

JPH1064285A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH1064285A
公开(公告)日：1998-03-06
申请号：JP21828196
申请日：1996-08-20
申请人： HITACHI LTD
发明人： KATO MASATAKA , TSUCHIYA OSAMU , YADORI SHOJI , TANAKA TOSHIHIRO , ADACHI TETSUO
IPC分类号： G11C17/00 , G11C7/00 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To make possible the application of a micro memory cell and reduce an area of a memory chip, by impressing a voltage to a source, a drain diffusion layer step by step when electrons are pulled from a floating gate electrode. SOLUTION: When electrons are pulled out from a floating gate electrode, a positive voltage is impressed to a diffusion layer opposite to a diffusion layer where the electrons are to be pulled, thereby to decrease a maximum voltage impressed between a source terminal and a drain terminal. Further, a positive voltage is impressed to a control gate electrode of a memory cell where the electrons are not pulled and a diffusion layer not in a pull-out direction is let to float. A write/erasure method for the memory cell which is not restricted by a voltage decrease inviting a problematic punch-through current between the source and drain when the memory cell is microminiaturized, in other words, not restricted by a decrease of a punch-through voltage is obtained, and a memory chip can be very small.

47. 发明专利

JPH056997A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH056997A
公开(公告)日：1993-01-14
申请号：JP18334591
申请日：1991-06-27
申请人： HITACHI LTD
发明人： OTSUKA FUMIO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , TSUCHIYA OSAMU , SUGIURA JUN
IPC分类号： H01L27/12 , H01L29/78 , H01L29/786
摘要： PURPOSE:To facilitate high integration even in the case of incorporating a level sensor or a timer by arranging the constitution such that a drain current flows to the transistor made in a semiconductor substrate when the gate potential on the semiconductor region made on the semiconductor substrate tops a certain value. CONSTITUTION:First source and drain regions 4 are provided on one main surface of a semiconductor substrate 1, and a first insulating film 2 is made on one main surface between these regions 4. A semiconductor region 3 is provided on the first insulating film 2, and second source and drain regions 7 are provided on the top of this region 3. A second insulating film 5 is provided on the main surface of the semiconductor region 3 between these regions 7, and a gate electrode 6 is provided on this insulating film 5. And by the gate potential added to a gate electrode 6, the substrate current flowing in the semiconductor region 3, in its turn, the potential of the substrate 1 in the semiconductor region 3 is changed, whereby the current flowing between the first source and drain is controlled. Hereby, a semiconductor device can be made in small occupancy area, and the degree of integration can be improved.

48. 发明专利

JPH01243461A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01243461A
公开(公告)日：1989-09-28
申请号：JP6943988
申请日：1988-03-25
申请人： HITACHI LTD
发明人： KAJITANI KAZUHIKO , TSUCHIYA OSAMU
IPC分类号： G11C11/418 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To equalize the coupling capacitance of word lines and data lines by crossing split word lines in the coupling sections of the split word lines and the word lines and bonding the memory cells of one and the other of the memory cells sharing a drain region with the split word lines, the word lines, in the same number or approximately the same number. CONSTITUTION:One and the other of memory cells sharing a drain region in a MOSFET for selecting addresses are bonded with adjacent split word lines in the same number or approximately the same number by crossing split word lines in the coupling sections of the split word lines DWLa1-DWLas+1, DWLb1-DWLbs as word lines WLa, WLb. Consequently, when the title device is viewed by one split word lines, the word lines WLa, WLb, the change of coupling capacitance is offset, and coupling capacitance among each data line DL and adjacent word lines WLa, WLb is brought to approximately the same electrostatic capacitance. Accordingly, array noises are suppressed, and a reading margin is improved.

49. 发明专利

JPH01145855A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01145855A
公开(公告)日：1989-06-07
申请号：JP30310787
申请日：1987-12-02
申请人： HITACHI LTD
发明人： SUWAUCHI NAOKATSU , TSUCHIYA OSAMU
IPC分类号： H01L21/768 , H01L21/28 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/43
摘要： PURPOSE:To prevent the formation of an Si deposit on a wiring and to prevent decrease in resistance value and wire breakdown, by introducing high concentration impurities in a polycrystalline silicon film, breaking the polycrystalline property, forming an amorphous silicon film, performing heat treatment for the amorphous silicon film, and forming a single crystal silicon film. CONSTITUTION:A polycrystalline silicon film 34B is formed on the entire surface of the upper part of an interlayer insulating film 30 so that the film is brought into contact with another semiconductor region 31 through a contact hole 33. High concentration n-type impurities are introduced into the polycrystalline silicon film 34B. As the n-type impurities, e.g., high concentration P (or As) is used. When the crystals are broken, the polycrystalline silicon film 34B is transformed into an amorphous silicon film 34C. Then, the amorphous silicon film 34C is patterned into a specified shape. The patterning is performed by, e.g., anisotropic etching such as RIE. Grains are formed in the amorphous silicon film 34C from a part of a memory selecting MISFET QS, which is single crystal silicon, in contact with the other semiconductor region by heat treatment. The grains grow and the size is increased. Thus the intermediate conductor film 34, in which single crystals are formed, is provided.

50. 发明专利

JPS6342164A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6342164A
公开(公告)日：1988-02-23
申请号：JP18507286
申请日：1986-08-08
申请人： HITACHI LTD
发明人： TSUCHIYA OSAMU , MIYAZAWA HIDEYUKI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To make it possible to form the electrode of a stacked capacitor readily, by forming a polycrystalline film for forming the electrode of the stacked capacitor, forming an oxidation preventing film having a specified shape on said film, and performing thermal oxidation with the oxidation preventing film as a mask. CONSTITUTION:An insulating film 8 such as, e.g., an SiO2 film, is formed on the surface of a polycrystalline silicon film 7. Then, an Si3N4 film 9 is formed on the insulating film 8. The Si3N4 film 9 is patterned by etching, and a specified shape is obtained. With the Si3N4 film 9 as a mask, the polycrystalline film 7 undergoes thermal oxidation. Thus an SiO2 film 10 which is continuous to the insulating film 8 is formed. The polycrystalline film 7 which has approximately the same shape as the Si3N4 film can be obtained. One electrode of a capacitor C is formed by the polycrystalline silicon film 7. Thus, the polycrystalline silicon film 7, which constitutes the electrode of the capacitor C and has the specified shape, can be readily formed at a steep step part.

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