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    • 41. 发明专利
    • ECHO CANCELLER
    • JPH0613938A
    • 1994-01-21
    • JP16868292
    • 1992-06-26
    • FUJITSU LTD
    • SAKAI YOSHIHIROKURIHARA HIDEAKIUTSUGI KIYOSHIKUGIMIYA JUNICHISAKAMOTO KEIZO
    • H04B3/20
    • PURPOSE:To attain talking without causing a noise sound or howling by forming the echo canceller in two stages, allowing the front stage to cancel an echo of a direct component and allowing the post stage to eliminate a reverberation component. CONSTITUTION:A tap coefficient of a filter of a 1st echo canceller 1 is selected so that the echo canceller 1 has an impulse response corresponding to a direct component inputted directly from a speaker 4 to a microphone 3. The direct component has a short reverberation time of the echo and number of taps is decreased. Furthermore, a 2nd echo canceller 2 erases a reverberation component having many tap numbers reflected in a wall or the like in a room unable to be eliminated by the 1st echo canceller 1. Then, the 1st echo canceller 1 erases the direct component having a largest component in the entire echo and having a short delay time, and when the output representing the result of elimination of the direct component is inputted to the 2nd echo canceller 2, the reverberation component being small having a large delay time is eliminated. Thus, the excellent echo cancellation quantity is attained from the start of the operation.
    • 45. 发明专利
    • FLOATING-POINT MULTIPLIER
    • JPS63189936A
    • 1988-08-05
    • JP2282987
    • 1987-02-03
    • FUJITSU LTD
    • KURIHARA HIDEAKI
    • G06F7/487G06F7/508G06F7/52
    • PURPOSE:To reduce the number of times of carry detection and to shorten arithmetic processing time by providing the titled multiplier with a rounding/ carry detecting circuit for detecting carry based on a carry signal obtained from a mantissa part and rounding. CONSTITUTION:A carry signal from a mantissa part arithmetic circuit 20, a mantissa part bit to be a multiplied result and a code bit from an exponential part arithmetic circuit 10 are supplied to the rounding/carry detecting part 30 to judge carry and rounding. The detecting circuit 30 corresponding to respective states, i.e. (1) when both carry and rounding are not included, (2) when only carry is generated, (3) when both rounding and carry are generated, and (4) when only rounding is executed, and controls selectors 291, 271 in the circuit 20 and the circuit 10. Consequently, the number of times of carry detection is only once, so that the arithmetic processing time can be shortened.