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1. 发明专利

JPH05313699A VOICE ENCODING AND DECODING DEVICE 失效
公开(公告)号：JPH05313699A
公开(公告)日：1993-11-26
申请号：JP11385592
申请日：1992-05-07
申请人： FUJITSU LTD
发明人： TANAKA YOSHIAKI , TANIGUCHI TOMOHIKO , UTSUGI KIYOSHI , KURIHARA HIDEAKI , SAKAI YOSHIHIRO
IPC分类号： G10L19/08 , G10L19/00 , G10L19/04 , G10L9/14 , G10L9/18
摘要： PURPOSE:To prevent a reproduced voice from deteriorating in quality as to the voice encoding and decoding device which is used to compress and transmits information of a voice signal. CONSTITUTION:In an encoding and decoding system having a voice encoding part which sends out the index of an optimum adaptive code vector selected from a 1st adaptive code book 11a and the frame electric power of an input speech signal and a voice decoding part which reads an adaptive code vector corresponding to the received index out of a 2nd adaptive code book 31a updated by the same method with the 1st adaptive code book 11a, a coefficient multiplying means 4 provided at the voice decoding part multiplies the read adaptive code vector by a coefficient (g) predetermined corresponding to the received frame electric power value to normalize the frame electric power value, finds a gain coefficient beta' by using a predetermined arithmetic means and the normalized frame electric power value, and multiplies the gain coefficient by the normalized adaptive code vector.

2. 发明专利

JPH01268337A INTERFACE CIRCUIT 失效
公开(公告)号：JPH01268337A
公开(公告)日：1989-10-26
申请号：JP9774288
申请日：1988-04-20
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI
IPC分类号： H04L13/08 , H04L13/10
摘要： PURPOSE:To improve the data transfer efficiency by providing a flag for showing whether unprocessed data exists or not, loading the data to a #1 register in case when a #2 register is free, and simultaneously, transferring it to the #2 register. CONSTITUTION:A #1 data store state flag generating means 6 for generating a flag for showing a data store state of a #1 register, a #2 data store state flag generating means 7 for generating a flag for showing a data store state of a #2 register are provided on the #1 register and the #2 register, respectively. In this state, when the #2 data store state flag generating means 7 is '0' for showing a fact that the #2 register 2 is free, data is loaded to the #1 register 1, and simultaneously, transferred to the #2 register. In such a way, the data is read out immediately in series from the #2 register and outputted, therefore, the data transfer efficiency can be improved.

3. 发明专利

JPH01241950A INTERFACE CIRCUIT 失效
公开(公告)号：JPH01241950A
公开(公告)日：1989-09-26
申请号：JP6875488
申请日：1988-03-23
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI
IPC分类号： H03M1/12 , H04L13/08 , H04L13/16
摘要： PURPOSE:To improve the data transmission efficiency by providing two registers connected in parallel with an input side line, with an input data written therein or read out therefrom and applying a clock alternately so as to send the content of the registers alternately. CONSTITUTION:Connecting 1st register 3 and 2nd register 4 in parallel with the input side line, and a clock is applied to a predetermined register when both the two registers 3, 4 are idle by a control signal from a control means 5 and then a clock is applied alternately to the 1st register 3 or the 2nd register 4 alternately and the content of the 1st register 3 and the 2nd register 4 is sent alternately to the output side line. Thus, when the two registers 3, 4 are idle, the data is written immediately to a predetermined register and sent to the output side line and the data transmission efficiency is improved.

4. 发明专利

JPH01240019A INTERFACE CIRCUIT 失效
公开(公告)号：JPH01240019A
公开(公告)日：1989-09-25
申请号：JP6756488
申请日：1988-03-22
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI
IPC分类号： H03M9/00
摘要： PURPOSE:To facilitate the reading and the writing of data by providing two input registers and two output registers, reading input data with a first and a second input registers for a frame serially, outputting them to a signal processor in parallel and allowing the first and the second output registers to act inversely to the above. CONSTITUTION:In case of data-inputting to a digital signal processor, data DATAin is inputted to a serial input register 21 while synchronizing with a clock CKI for a synchronous signal SYNCI corresponding to the control of a serial input control circuit 23. The control circuit 23 generates the clock when data-writing to a register 21 is ended, and the data head in the register 21 is inputted to an input register 22 in parallel. The data outputted from the DSP are inputted to an output register 25 in parallel corresponding to a load command from the DSP. An serial output control circuit 27 makes the data output from a register 26 while synchronizing with a clock CKO. Consequently, when the idle time between frames is short, it does not interfere with the writing and the reading of the data.

5. 发明专利

JPH01218216A INTEGRATION TYPE A/D CONVERTER 失效
公开(公告)号：JPH01218216A
公开(公告)日：1989-08-31
申请号：JP4224888
申请日：1988-02-26
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI
IPC分类号： H03M1/52
摘要： PURPOSE:To execute the high speed of an A/D converting speed by providing a means to convert the analog unknown voltage to the time corresponding to the size, measure the time with a clock counting and digitize it. CONSTITUTION:A first integration circuit 22 integrates the unknown voltage of an analog inputted and outputs the voltage to rise by the inclination in accordance with the value. For a second integration means 28, after a first constant voltage is supplied for a prescribed time, a second constant voltage larger than the voltage is supplied, these voltages are integrated and the voltage to fall by the inclination in accordance with the value is outputted. For an adder 29, at the time of integrating first and second constant voltages, a third constant voltage and a fourth constant voltage smaller than this are respectively supplied and these voltages and the output of the circuit 28 are added. For a comparator 23, the output voltage of the circuit 22 and the adder 29 is compared and when both are coincident, an instruction signal is generated. A counter 31 counts the pulse value until an instruction signal is generated and the digital value corresponding to the value of the unknown voltage is outputted from a terminal 33 based on the value.

6. 发明专利

JPS63226125A DIGITAL CONTROL TYPE AGC EQUALIZER 失效
公开(公告)号：JPS63226125A
公开(公告)日：1988-09-20
申请号：JP6041587
申请日：1987-03-16
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI
IPC分类号： H04B3/06
摘要： PURPOSE:To quickly correct a gain step adjusted too lower by increasing the gain step of an equalizer whose maximum gain is higher by one step at the end of gain updating and restoring the state at the end of original gain revision or applying gain updating again in response to the result of comparison of the level between the peak of the output signal and a desired value. CONSTITUTION:Peak detection means 3, 4 are provided, which detect whether or not the peak of the output signal of an equalizer is a desired value or below while the gain of other equalizer whose maximum gain is high in the rank of the n-th is not maximum and the gain is increased by one step than that at the end of gain updating, at the end of gain updating of an equalizer whose maximum gain is in the (n+1)-th rank (n=1, 2..., m-1) among m-set (m is an integral number being 2 or over) equalizers. Moreover, control means 5-7 completing the gain updating of the equalizer whose maximum gain is high in the (n+1)-th rank in response to the output signal of the peak detection means 3, 4 or retrying the gain updating of other equalizer, are provided. Thus, in the case of the gain decreased too much, the gain is corrected quickly.

7. 发明专利

JPH0876970A '0' DETECTION TYPE CODE CONVERTER AND ITS CODE CONVERSION METHOD 失效
公开(公告)号：JPH0876970A
公开(公告)日：1996-03-22
申请号：JP20837894
申请日：1994-09-01
申请人： FUJITSU LTD
发明人： ITO MASATO , UTSUGI KIYOSHI , NISHIIKE RIKA
IPC分类号： G06F5/00
摘要： PURPOSE: To speed up code conversion in an '0' detection type code converter and its code conversion method for converting an RBC into an SBC. CONSTITUTION: In the code conversion method for the code converter for converting an RBC into an SBC, '0' detection for finding out whether the codes of respective digits other than the least significant digit of the RBC are '0' or not is executed, and when the code of a self-digit is other than '0' in the case of converting the code of each digit in the RBC into the code of each digit of the SBC, the code information of a just upper digit if the upper digits exists is referred and prescribed conversion is executed based upon the referred information. When the code of the self-digit is '0', the code information of the upper digit and the code information of a lower digit other than '0' on the lower digit side if the lower digits exist are referred and prescribed conversion is executed based upon these information.

8. 发明专利

JPH0730438A VITERBI DECODING METHOD 失效
公开(公告)号：JPH0730438A
公开(公告)日：1995-01-31
申请号：JP19428493
申请日：1993-07-09
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI , KATO MASAKO , ITO MASATO
IPC分类号： H04L1/00 , H03M13/23 , H03M13/12
摘要： PURPOSE:To sharply reduce operation volume to be required for branch metric calculation in respect to a viterbi decoding method for decoding a receiving sequence encoded by convolusion by means of the arithmetic processing of a processor. CONSTITUTION:In this Viterbi decoding method for decoding a receiving sequence encoded by convolution by means of a processor, a branch metric value corresponding to each state is tabulated and stored in a memory 1, and at the time of executing operation for selecting a remaining pass, the branch metric value is read out front the memory 1 and used.

9. 发明专利

JPH04271431A OPERATION CONTROL SYSTEM 失效
公开(公告)号：JPH04271431A
公开(公告)日：1992-09-28
申请号：JP3118991
申请日：1991-02-27
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI
IPC分类号： G06F7/00 , G06F9/22 , G06F9/30
摘要： PURPOSE:To execute the processing, where the classification of the next operation instruction must be selected in accordance with the result of the preceding operation, without using a branch instruction in the operation control system of an information processor. CONSTITUTION:An operation circuit 3 which selectively executes plural kinds of operation by an indication, a status register 5 to which status information indicating the processing state is set, and an operation control circuit 6 which indicates the classification of operation to be next executed by the operation circuit 3 based on status information set to the status register 5 are provided, and a conditional operation instruction inclusively indicating plural kinds of operation is used to start the operation circuit 3, and the operation classification to be executed of the operation circuit is automatically set based on status information.

10. 发明专利

JPH04245718A VECTOR QUANTIZING SYSTEM 失效
公开(公告)号：JPH04245718A
公开(公告)日：1992-09-02
申请号：JP2773691
申请日：1991-01-30
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI , YAMASHITA NAMI
IPC分类号： H03M7/30
摘要： PURPOSE:To offer a vector quantizing system capable of improving an operation speed without sharply increasing the size of an arithmetic circuit in respect to a system for executing vector quantization by using a code book. CONSTITUTION:This vector quantizing system is provided with plural low frequency arithmetic circuits 11, 12, a high accurate arithmetic circuit 2 and the code book 3 for storing plural vector data having high accuracy and the circuits 11, 12 compare the upper digit part of data obtained by the data of the code book 3 into the number of the arithmetic circuits with the upper digit part of input data and select data minimizing errors as optimum vector candidates. Then the circuit 2 compares all the digit data of respective optimum vector candidates selected by respective circuits 11, 12 with all the digits of the input data and selects the code book data minimizing the error as an optimum vector.

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