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1. 发明专利

JPH08147192A DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPH08147192A
公开(公告)日：1996-06-07
申请号：JP29121894
申请日：1994-11-25
申请人： FUJITSU LTD
发明人： KURIHARA HIDEAKI , KATAYAMA HIROSHI
IPC分类号： G06F11/30
摘要： PURPOSE: To surely detect the runaway state of an infinite loop or the like and to speedily recover normal processing by inputting specified codes at fixed intervals, comparing them with coincidence confirmation data stored in advance and generating an abnormality generating signal when any non-coincidence is detected. CONSTITUTION: A core processor part 1 corresponding to the conventional digital signal processor(DSP) previously stores the specified codes and outputs these specified codes at the fixed intervals. An abnormality monitoring part 2 inputs these specified codes and compares them with the coincidence confirmation data stored in advance. When any non-coincidence is detected as a result of this comparison, the abnormality generating signal is generated and applied to the core processor part 1. Thus, the core processor part 1 is recovered from the runaway state to a normal state based on that abnormality generating signal. In order to recover the core processor part 1 to the normal state, processing such as substituting a PC initial value from a specified instruction code address to a built-in program counter or the like is performed corresponding to the abnormality generating signal.

2. 发明专利

JPH06342450A MATRIX MULTIPLIER 失效
公开(公告)号：JPH06342450A
公开(公告)日：1994-12-13
申请号：JP13018293
申请日：1993-06-01
申请人： FUJITSU LTD
发明人： OBARA HIROSHI , KURIHARA HIDEAKI
IPC分类号： G06F17/16 , G06F15/347
摘要： PURPOSE:To provide the matrix multiplier for efficiently multiplying matrixes at a microprocessor or a DSP concerning the device for performing the multiplication of matrixes. CONSTITUTION:The matrix multiplier for providing JAXKB matrixes CJA and CKB by multiplying JAXKA matrixes AJA and AKA and JBXKB matrixes BJB and BKB is provided with a program control part 1 for controlling the execution of a matrix multiplying instruction CJA,KB=AJA,KAXBJB,KB with a program, address generation part 2 for generating an address to be used by the program, sum of product arithmetic part 3 for calculating the sum of products between the elements of the matrixes AJA and AKA and the elements of the matrixes BJB and BKB, and memory 4 for previously storing the respective elements of the matrixes AJA and AKA and the matrixes BJB and BKB and for storing the respective elements of the calculated matrixes CJA and CKB.

3. 发明专利

JPH05307400A 失效
公开(公告)号：JPH05307400A
公开(公告)日：1993-11-19
申请号：JP11269792
申请日：1992-05-01
申请人： FUJITSU LTD
发明人： KURIHARA HIDEAKI , SAKAI YOSHIHIRO , UTSUGI KIYOSHI
IPC分类号： G10L19/08 , G10L19/00 , G10L19/04 , G10L19/12 , G10L9/14 , G10L9/18
摘要： PURPOSE:To prevent a quality degradation of voices by selecting optimum driving sound source signals when the power of reproduced signals generated from optimum driving sound source signals is more than the threshold value, selecting a zero when the power is less than the threshold value and giving it to an adaptive coding table. CONSTITUTION:A synthesis filter 3 generates reproduced signals from optimum driving source signals in the coder side of a voice coding system in which pitch search and coding table search is performed to obtain optimum driving sound source signals using an adaptive coding table 1 and a fixed coding table 2. And a zero replacement discriminating circuit 4 selects optimum driving sound source signals when the power of reproduced signals is more than the threshold value, selects zero when the power is less than the threshold value and gives to the adaptive coding table 1 through a frame delaying unit 5. Thus, a quality degradation of voices is eliminated at the rise of voices by updating the components of the adaptive coding table, which is used to generate a pitch periodic driving sound source, to zero when the optimum driving sound source signals, which are used to update the table, are practically zero.

4. 发明专利

JPH05158497A VOICE TRANSMITTING SYSTEM 失效
公开(公告)号：JPH05158497A
公开(公告)日：1993-06-25
申请号：JP32336891
申请日：1991-12-06
申请人： FUJITSU LTD
发明人： OTA TAKASHI , TANIGUCHI TOMOHIKO , TANAKA YOSHIAKI , KURIHARA HIDEAKI , KATO MASAKO
IPC分类号： G10L19/08 , G10L19/00 , G10L19/12 , H03M7/30
摘要： PURPOSE:To generate a noise code book not only with a space rate but also with a code vector, which can compensate a cycle component not sufficiently expressed even by the applied code book by the noise code notebook, by sequentially arranging the sparse rates of respective noise code vectors from sparseness to denseness. CONSTITUTION:An N-dimensional initial sparse vector to express a reference noise sequence and a sparse delta vector to express a delta noise sequence are prepared as a sparse delta code book beforehand. Then, the number of the samples of delta code vectors to be applied is fixed to two samples, the number of samples canceled with a preceding index and the number of samples newly generated at the position of a value '0' are allocated one by one, and an impulse code vector is virtually generated by shifting sample positions one by one. Then, by applying a prescribed restriction condition, concerning the code vectors of indexes from Nth to (2N-1)th, the noise code book from sparseness to denseness can be formed at the increase rate of two samples with two indexes.

5. 发明专利

JPH05158496A VOICE CODING DEVICE 失效
公开(公告)号：JPH05158496A
公开(公告)日：1993-06-25
申请号：JP32336791
申请日：1991-12-06
申请人： FUJITSU LTD
发明人： KATO MASAKO , TANIGUCHI TOMOHIKO , KURIHARA HIDEAKI , OTA TAKASHI , AMANO FUMIO
IPC分类号： G10L19/08 , G10L19/04 , G10L19/12 , H03M7/30
摘要： PURPOSE:To prevent characteristics from being degraded when inputting fine voice signals by selecting a zero vector as an optimum code word again when error signal power exceeds input voice signal power. CONSTITUTION:When preparing a code notebook by generating a noise sequence, a vector (defined as C0), for which all the elements of the code word are zero, is given to a noise code notebook 2. When the optimum code word is completely retrieved, an error power evaluation part 5 calculates error signal power Ec of an auditive sense weighted regenerative signal obtained by the optimum code word and a quantized optimum code gain and the input voice signal and judges the levels of this error signal power Ec and input voice signal power (AX) . When the error signal power Ec exceeds the input voice signal power (AX) , the selected code word C is abandonned and the code vector Co, for which all the elements are zero, is selected as the optimum code word again. Thus, noise generation is prevented.

6. 发明专利

JPH0511799A VOICE CODING SYSTEM 失效
公开(公告)号：JPH0511799A
公开(公告)日：1993-01-22
申请号：JP16727091
申请日：1991-07-08
申请人： FUJITSU LTD
发明人： KATO MASAKO , TANAKA YOSHIAKI , TANIGUCHI TOMOHIKO , KURIHARA HIDEAKI , AMANO FUMIO
IPC分类号： G10L19/00
摘要： PURPOSE:To perform faster voice coding by reducing computing operation during evaluating errors while minimizing the degradation of synthesized voice. CONSTITUTION:A driven vector 102 is selected by a code book memory means 101. A voice synthesizing means 103 synthesizes voice in accordance with linear prediction analysis by using the driven vector 102 as an input element. A thinning-out mean 106 performs individual thinning-out of the element value of an input voice vector 105 and the element value of a synthesized voice vector 104 at certain intervals. An error evaluating means 109 performs square error evaluation of a thinned-out input voice vector 107 and a thinned-out synthesized voice vector 108. The above processings are repeated for every driven vector 102 so that the input voice vector 105 is coded in accordance with parameters which brings the synthesized voice vector with the minimum square error (maximum correlation value).

7. 发明专利

JPH04277800A VOICE ENCODING SYSTEM 失效
公开(公告)号：JPH04277800A
公开(公告)日：1992-10-02
申请号：JP4008291
申请日：1991-03-06
申请人： FUJITSU LTD
发明人： OTA TAKASHI , TANIGUCHI TOMOHIKO , TANAKA YOSHIAKI , KURIHARA HIDEAKI , AMANO FUMIO
IPC分类号： G10L19/08 , G10L19/00 , G10L19/04
摘要： PURPOSE:To enable real-time processing by reducing the arithmetic quantity. CONSTITUTION:The voice encoding system identifies the target vector of an input voice with the vector generated by processing a signal vector, generated by delaying the residue signal of a precedent frame, by linear predictive weighted filtering and the vector generated by processing a residue signal read out of a code book (70) by linear predictive weighted filtering. The same sample position of all residue signal vectors in the code book (70) are forcibly set to zero. When the residue vectors are weighted and filtered, the arithmetic for the sample positions of the zero value of the residue signal vectors is omitted.

8. 发明专利

JPH01291365A DIGITAL SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH01291365A
公开(公告)日：1989-11-22
申请号：JP12085888
申请日：1988-05-18
申请人： FUJITSU LTD
发明人： KURIHARA HIDEAKI
IPC分类号： G06F17/10
摘要： PURPOSE:To diminish a processing delay on the side of a decoder by constituting the title circuit so that a counter is initialized automatically by a hardware, when said circuit has become a state that an interruption processing is executed at the time of rise of a frame signal. CONSTITUTION:The first storage means 640 stores an initial value of a counter 610, and the second storage means 650 stores a prescribed number of data which are inputted in a prescribed operation processing period. In this state, a comparing means 600 compares a value which has counted up a clock of an output of an input/output control part 630 and an output of the second storage means 650, and when both of them have coincided, a control signal for writing an output of the first storage means 640 in the counter is outputted. Accordingly, even if said circuit becomes a state that an interruption processing is executed at the time of rise of a frame signal, the counter 610 is initialized automatically by a hardware. In such a way, a processing delay on the side of a decoder is diminished.

9. 发明专利

JPH01280936A CODING/DECODING PROCESSING CONTROL SYSTEM 失效
公开(公告)号：JPH01280936A
公开(公告)日：1989-11-13
申请号：JP10989288
申请日：1988-05-07
申请人： FUJITSU LTD
发明人： KURIHARA HIDEAKI
IPC分类号： H04N19/00 , H04B14/04 , H04N19/42 , H04N19/423 , H04N19/426 , H04N19/85
摘要： PURPOSE:To prevent noise due to fluctuation of synchronization of a received coded data by transferring a coded data from a reception buffer to a 1st data area if the 1st data area is not in use and transferring the coded data from the reception buffer to a 2nd data area when the 1st data area is busy. CONSTITUTION:When an interruption flag is set before the start of coding processing, a coded data is transferred from the reception buffer 3 to the 1st data area 4. When an interrupt flag is set before decoding processing, if the 1st data area 4 is idle, the coded data is transferred and transferred to the 2nd data area 5 when not idle and the coded data is transferred from the 2nd data area 5 to the 1st data area 4 by the end of decoding processing. Thus, the memory capacity is saved and the fluctuation of frame synchronization of the received coded data due to the state change of a transmission line is absorbed by the 1st and 2nd data areas 4, 5, then the generating of noise is prevented.

10. 发明专利

JPS63262575A INTEGRATED CIRCUIT FOR PROCESSING DIGITAL SIGNAL 失效
公开(公告)号：JPS63262575A
公开(公告)日：1988-10-28
申请号：JP9774587
申请日：1987-04-20
申请人： FUJITSU LTD
发明人： KURIHARA HIDEAKI , MATSUMURA TOSHIHIKO
IPC分类号： G01R31/28 , G06F17/10 , H03K19/00
摘要： PURPOSE:To return a DSP testing mode to a usual operation mode even when an external input resetting signal changes by noise, by using the external input resetting signal as the control signal changing over the DSP testing mode and the usual operation mode. CONSTITUTION:A mode change-over circuit 3 inputs an external input resetting signal and a master clock and outputs not only the external input resetting signal as a mode output signal through a terminal 9 but also the output signal of a NAND circuit 8 as an internal resetting signal through a terminal 10. The terminal 10 is connected to a memory circuit containing the first memory storing a program at the time of an usual operation mode and the second memory storing a testing program to supply the internal resetting signal. The terminal 9 is connected to a selector 14 and outputs either one of the orders of the first and second memories to an order decorder 15 in accordance with the external input resetting signal to select a mode.

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