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    • 34. 发明专利
    • WRITING/ERASING METHOD OF SEMICONDUCTOR MEMORY
    • JPH06169073A
    • 1994-06-14
    • JP31958992
    • 1992-11-30
    • HITACHI LTD
    • USHIYAMA MASAHIROKATO MASATAKATANAKA TOSHIHIROADACHI TETSUOKUME HITOSHIOJI YUZURUTAJI SHINICHI
    • H01L21/8247H01L27/115H01L29/788H01L29/792
    • PURPOSE:To draw out electrons and positive holes stored in a gate insulating film to an electrode side or a substrate side, suppress the deterioration of the gate insulating film caused by a re-writing operation and improve a re-writing strength by a method wherein writing or erasing pulses are time-divided and pulses whose polarities are opposite to each other are applied. CONSTITUTION:For instance, after pulses of -7V and +3.3V are applied t8 a control gate electrode 7 and a source 8 respectively for 1 microsecond while a drain 9 is opened and a substrate 1 is grounded, successively pulses of 6V and 0V are applied to the control gate electrode 7 and the source 8 respectively for 0.5 microsecond while the drain 9 is opened and the substrate 1 is grounded. After the above mentioned bidirectional stresses are applied for 10 cycles, an operation for confirming a threshold is performed. Thus letting one re-writing be composed of one writing, one erasing and the number of the re-writing operations are repeated. With this constitution, electrons and positive holes injected into an insulating film 6 are discharged, quantities of electrons and positive holes captured in the insulating film 6 are reduced and the characteristic fluctuation of the insulating film 6 is suppressed, so that the breakdown strength of the insulating film 6 can be improved.