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21. 发明专利

JPH06112196A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06112196A
公开(公告)日：1994-04-22
申请号：JP25694792
申请日：1992-09-25
申请人： TOSHIBA CORP
发明人： IIJIMA TADASHI , USHIKU YUKIHIRO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/3213 , H01L23/52
摘要： PURPOSE:To make it possible to form a coating which covers the sides of a wiring after the removal of a resist by installing an etching stopper layer on a wiring top layer designed to cover the top of the wiring and using a resist only when a wiring pattern is formed on this etching stopper layer and then removing the resist. CONSTITUTION:A Cu layer 25, which is used as a wiring material, is deposited on a TiN layer 24 deposited on an Sin. 11. A TiN layer 26 is further deposited on the layer 25, thereby forming a C layer 28 as an etching stopper layer. Then, a wiring pattern 28' of the C layer is formed with a formed photoresist 29 as a mask and then the photoresist 29 is removed. Furthermore, the TiN layer 26, the Cu layer 25, the TiN layer 24 and the TIN layer are patterned one after another, thereby forming a TiN film 13, a TiN film 14, a Cu wiring part 15 and a TiN film 16. A TiN layer 27 is deposited on the whole surface where anisotropic etching is carried out so that a TiN film 17 may be formed. This construction makes it possible to provide high reliability.

22. 发明专利

JPH05183160A SEMICONDUCTOR DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH05183160A
公开(公告)日：1993-07-23
申请号：JP34563091
申请日：1991-12-26
申请人： TOSHIBA CORP
发明人： NISHIYAMA AKIRA , USHIKU YUKIHIRO
IPC分类号： H01L29/43 , H01L21/28 , H01L29/78
摘要： PURPOSE:To provide a semiconductor device wherein contact resistance is not increased even though the device is made finer. CONSTITUTION:There are provided on a silicon substrate 1 a gate electrode 4 formed through a gate oxide film 3, a source-drain diffusion layer 6 formed on the surface of the silicon substrate 1 oppositely to the gate electrode 4, a source-drain electrode 9 formed on the source-drain diffusion layer 6, and a Si-Ge mixed crystal layer 8 displaced between the source-drain electrode 9 and the source-drain diffusion layer 6.

23. 发明专利

JPH04123439A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04123439A
公开(公告)日：1992-04-23
申请号：JP24250890
申请日：1990-09-14
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To generate no matching deviation between the source/drain regions and a gate electrode so as to form a minute element by a method wherein a dummy gate of the same shape is formed in a gate electrode formation scheduled region, an impurity is introduced with the dummy gate as a mask for forming the source/drain regions, the dummy gate is removed by etching to form a groove, and a gate electrode material is buried into the groove. CONSTITUTION:An oxide film 2 is formed on the surface on an n-type silicon substrate 1, and a resist pattern of a gate electrode, that is, a dummy gate 3 is formed. Boron ions are implanted to form the source/drain regions 4. Next, a wafer is dipped in an aqueous solution of hydrosilicofluoric acid saturated with silica and l is added, and an SiO2 film 5 is formed. The dummy gate 3 is removed, boron irons are implanted as a channel impurity to obtain a sharp channel profile. A gate oxide film 6 is formed, polysilicon 7 is deposited on the part of the removed dummy gate 3 and after phosphorus is diffused, reactive ion etching is performed so as to bury polysilicon 7 only in the part of the removed dummy gate.

24. 发明专利

JPH01239873A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01239873A
公开(公告)日：1989-09-25
申请号：JP6567688
申请日：1988-03-22
申请人： TOSHIBA CORP
发明人： MIHASHI TAKASHI , USHIKU YUKIHIRO
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To enable flattening an interlayer insulating film easily formed on lower layer windings and to enable preventing upper layer windings from breaking, for heightening the reliability, by providing dummy patterns separate from wiring patterns in a region where no wiring patterns for the underlying windings exist. CONSTITUTION:This semiconductor integrated circuit device has multilayer interconnection structure. And, patterns constituting lower layer windings and elements comprise patterns 11, 12 constituting the wiring and elements and provided at a specified distance separated from each other, and dummy patterns 310, 320 provided separately at a specified distance from the patterns 11, 12 constituting those wirings and elements, in the region where the patterns 11, 12 constituting the wirings and elements do not exist. For example, the said dummy patterns 310, 320 are formed so as to meet the specified design criteria with the lower layer windings 11, 12 and the upper layer windings 21, 22, and the distance between patterns opposing each other out of the patterns 11, 12, 310, 320 is made nearly equal to the specified minimum dimension.

25. 发明专利

JPS6319843A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6319843A
公开(公告)日：1988-01-27
申请号：JP16370886
申请日：1986-07-14
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO
IPC分类号： H01L21/8238 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L27/092
摘要： PURPOSE:To bring down the high level of an output buffer as low as possible and to perform a high speed switching operation by a method wherein one or a plurality of diodes, which are formed on the same substrate, are connected in series to the part located between an earthing wire and the output terminal of the output buffer of a CMOS semiconductor integrated circuit. CONSTITUTION:The output terminal 6 of a CMOS integrated circuit device 1 is connected to the input of a TTL circuit device. In this case, four diodes 7 formed on the same substrate are connected between the output terminal 6 of the output buffer 3 of the CMOS integrated circuit device 1 and an earthing wire. When the internal potential of said diodes is set at 0.7 V, the potential of the four diodes becomes 2.8V, and when the potential of said output terminal exceeds 2.8V, the diodes are turned ON, and the voltage of said output drops to 0-2.8V. As a result, the potential is to be changed from 2.8V to 1.4V in order to bring high level to low level, so the switching operation can be performed at the speed higher than the case where potential is changed from 5V to 1.4V.

26. 发明专利

JPS6161452A Cell structure of complementary mos 失效
标题翻译：补充MOS的细胞结构
公开(公告)号：JPS6161452A
公开(公告)日：1986-03-29
申请号：JP18281184
申请日：1984-09-03
申请人： Toshiba Corp
发明人： USHIKU YUKIHIRO
IPC分类号： H01L27/08 , H01L21/82 , H01L27/118 , H01L29/78
CPC分类号： H01L27/11807
摘要： PURPOSE:To obtain a cell having a structure which is highly resistant to latch-up, by a method wherein a space enabling the disposition of four or more contact holes with gate electrodes in the direction of a channel width is provided between a P-channel transistor and an N-channel transistor. CONSTITUTION:Gate electrodes 4 inside an N diffused layer 2 in a P welt 1 and inside a P diffused layer 3 on an N substrate are expanded so that four contact holes can be disposed. Thereby the base width 8 of a horizontal- type parasitic PNP bipolar is increased and thus a current gain is reduced. As the result, latch-up withstanding voltage is increased.
摘要翻译：目的：为了获得具有高抗闩锁性的结构的电池，通过这样的方法，可以在P沟道之间设置能够在沟道宽度方向上配置具有栅电极的四个或更多个接触孔的空间晶体管和N沟道晶体管。构成：N基板中的P层1和P +扩散层3内的N +扩散层2内的栅电极4被扩大，从而可以设置四个接触孔。因此，水平型寄生PNP双极的基极宽度8增加，因此电流增益减小。结果，闩锁耐受电压增加。

27. 发明专利

JPS59197151A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59197151A
公开(公告)日：1984-11-08
申请号：JP6997283
申请日：1983-04-22
申请人： Toshiba Corp
发明人： AKIBA HIROYUKI , USHIKU YUKIHIRO
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118
CPC分类号： H01L27/118
摘要： PURPOSE:To control an IC device easily by previously preparing a wafer, to which a master process is completed beforehand, and using one or plural fundamental chips in response to the scale of an IC to be prepared when single or plural kinds of fundamental unit elements are formed on the wafer. CONSTITUTION:Fundamental chips 5 to which active elements 2 and circuit elements 3 for inputs/outputs are formed are shaped previously through a chip isolation region 4. On the other hand, regions in which one chips 5 are mounted are formed surrounded by scribing lines 6 and a plurality of pads 1 are shaped previously to the peripheral sections of the regions in a master wafer loading these chips 5. Accordingly, the number of the fundamental chips is selected in response to the scale of an IC circuit to be prepared, and the chips are fixed onto loading regions, and mutually connected desirably by using the pads 1. That is, wirings in the fundamental chips and wirings in the isolation region are formed separately, and the burden of a computer system for the wirings is lightened.
摘要翻译：目的：通过预先准备预先完成主处理的晶片，并且在单个或多种基本单元元件的响应于要制备的IC的规模时使用一个或多个基本芯片来容易地控制IC器件形成在晶片上。构成：通过芯片隔离区域4预先形成用于输入/输出的有源元件2和电路元件3的基本芯片5。另一方面，其中安装有一个芯片5的区域被划线6包围并且多个焊盘1预先成形为装载这些芯片5的母晶片中的区域的周边部分。因此，响应于要准备的IC电路的规模选择基本芯片的数量，并且芯片被固定在加载区域上，并且期望地通过使用焊盘1相互连接。即，隔离区域中的基本芯片和布线中的布线分别形成，并且用于布线的计算机系统的负担被减轻。

28. 发明专利

JP2007227953A Semiconductor wafer, manufacturing method thereof, method and device for manufacturing semiconductor device 有权
标题翻译：半导体晶体管及其制造方法，制造半导体器件的方法和器件
公开(公告)号：JP2007227953A
公开(公告)日：2007-09-06
申请号：JP2007096900
申请日：2007-04-02
申请人： Toshiba Corp , 株式会社東芝
发明人： IWASE MASAO , NITTA SHINICHI , MIYASHITA MORIYA , SUGAMOTO JIYUNJI , YAMADA KOREI , NAGANO HAJIME , TANZAWA KATSUJIRO , UDO SUKEMUNE , NADAHARA SOICHI , TSUCHIYA NORIHIKO , MATSUSHITA HIROSHI , USHIKU YUKIHIRO , ARIKADO TSUNETOSHI , OKUMURA KATSUYA
IPC分类号： H01L21/02
摘要： PROBLEM TO BE SOLVED: To manufacture a semiconductor device of high throughput by suppressing variation in manufacture among wafers, using a circular wafer in which neither notch nor orientation flat is present. SOLUTION: A semiconductor wafer 60 comprises a wafer of which a first main surface on which a semiconductor element is formed is circular, a bevel part formed on the outer periphery of the wafer, and a reference ID mark 61 which is provided to the bevel part to show crystal orientation of the wafer. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过抑制晶片之间的制造变化来制造高通量的半导体器件，使用其中不存在凹口和取向平面的圆形晶片。解决方案：半导体晶片60包括其上形成有半导体元件的第一主表面是圆形的晶片，形成在晶片的外周上的斜面部分和参考ID标记61，斜面部分显示晶片的晶体取向。版权所有（C）2007，JPO＆INPIT

29. 发明专利

JP2006222447A SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：JP2006222447A
公开(公告)日：2006-08-24
申请号：JP2006107083
申请日：2006-04-10
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/8247 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/092 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor apparatus in which insulation films are practically equally high in the element isolation region, which has multiple single crystal semiconductor layers with different film thicknesses, and which has a structure enabling easy minute wiring, and to provide its manufacturing method. SOLUTION: A semiconductor apparatus integrates semiconductor devices having multiple SOI-Si layer thicknesses, wherein their height in the device isolation region 13 from the surface of the semiconductor substrate is in effect equal. Further, the multiple SOI-Si layers 14 and 15 with properly different heights are formed after the device isolation region 13 with an even height has been formed on a semiconductor substrate 11. Thus, the device isolation region 13 with a practically equal height from the semiconductor substrate 11 can be achieved while a desirable device region with a different SOI-Si layer thickness can be formed. Further, the height of a gate electrode formed on the primary SOI-Si layer from the semiconductor substrate surface is made equal to the height of a gate electrode formed on the secondary SOI-Si layer from the semiconductor substrate surface. COPYRIGHT: (C)2006,JPO&NCIPI

30. 发明专利

JP2006157029A Manufacturing system and method of semiconductor device 有权
标题翻译：制造系统和半导体器件的方法
公开(公告)号：JP2006157029A
公开(公告)日：2006-06-15
申请号：JP2005351128
申请日：2005-12-05
申请人： Toshiba Corp , 株式会社東芝
发明人： USHIKU YUKIHIRO , OGAWA AKIRA , KAKINUMA HIDENORI , SHUDO SHUNJI , ABE MASAYASU , AKIYAMA TATSUO , KOMATSU SHIGERU
IPC分类号： H01L21/02 , C23C16/52 , H01L21/00 , H01L21/3065 , H01L21/31 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing system of a semiconductor device which properly manages a maintenance interval of the individual processing apparatus, extends an operating time of each processing apparatus, reducing a wafer inspection process performed at the stage of completing each semiconductor manufacturing process, and shortens a manufacturing process period of a semiconductor device. SOLUTION: This system is provided with a processor 14 for executing process treatment using a semiconductor substrate 17, a self-diagonostic system 11a for receiving device information from the processor 14 and calculating an estimated quality value of the process treatment, an inspection device 19 for inspecting the result of the process treatment, and a computer 11. The computer 11 compares an inspection result and an estimated quality value, and maintains a parameter of the self-diagonostic system when the estimated quality value is valid and changes a parameter of the self-diagonostic system when the estimated quality value is invalid. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供适当地管理各个处理装置的维护间隔的半导体装置的制造系统，延长每个处理装置的操作时间，减少在完成每个处理装置的阶段执行的晶片检查处理半导体制造工艺，缩短半导体器件的制造工艺周期。解决方案：该系统设置有用于执行使用半导体衬底17的处理处理的处理器14，用于从处理器14接收设备信息并计算处理处理的估计质量值的自我对角线系统11a，检查用于检查处理结果的装置19和计算机11.计算机11将检查结果与估计的质量值进行比较，并且当估计的质量值有效时维持自我对角系统的参数，并且改变参数的估计质量值无效的自我对角线系统。版权所有（C）2006，JPO＆NCIPI

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