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21. 发明专利

JP2006155700A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006155700A
公开(公告)日：2006-06-15
申请号：JP2004341475
申请日：2004-11-26
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： OSADA KENICHI , KAWAHARA TAKAYUKI
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C11/5678 , G11C13/0004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/74 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a technology which can suppress variations of values after writing to the minimum, and facilitate multiple value coding in a semiconductor device such as a phase transition memory. SOLUTION: The semiconductor device has; a memory cell including a storage element (phase transition element) which stores information by change of a status with temperature; an input and output circuit; and means, when writing data, to perform a set operation (step S101), then perform write operation of desired data (step S102), measure a resistance value of the storage element by a verify operation (step S103), and when the resistance value is not in the desired range, perform write operation for the second time by changing applying voltage to the storage element (steps S105 and S108) after performing the set operation again (steps S104 and S107). COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在写入到最小值之后抑制值的变化的技术，并且促进诸如相变存储器的半导体器件中的多值编码。
解决方案：半导体器件具有：存储单元，其包括通过温度变化来存储信息的存储元件（相变元件）; 一个输入和输出电路; 并且当写入数据时执行设定操作（步骤S101），然后执行所需数据的写入操作（步骤S102），通过验证操作测量存储元件的电阻值（步骤S103），并且当电阻值不在期望的范围内，再次执行设定操作之后，通过改变向存储元件施加电压（步骤S105和S108），第二次执行写入操作（步骤S104和S107）。版权所有（C）2006，JPO＆NCIPI

22. 发明专利

JP2005050514A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2005050514A
公开(公告)日：2005-02-24
申请号：JP2004249069
申请日：2004-08-27
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , KAWAJIRI YOSHIKI , AKIBA TAKESADA , HORIGUCHI SHINJI , WATABE TAKAO , KITSUKAWA GORO , KAWASE YASUSHI , TACHIBANA RIICHI , AOKI MASAKAZU
IPC分类号： H01L27/04 , G11C11/407 , H01L21/822 , H01L21/8234 , H01L27/088 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To reduce current consumption during standing-by in a semiconductor integrated circuit using a fine MOS transistor.
SOLUTION: A voltage between the gate and source of the first MOS transistor in case both first and second MOS transistors are held off (T1=VC and I1=VC) is made into the polarity inverse from the polarity of a voltage between the gate and source of the first MOS transistor in case the first MOS transistor is on and the first MOS transistor is changed from off to on after the second MOS transistor is changed from off to on.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了减少使用精细MOS晶体管的半导体集成电路中的待机时的电流消耗。解决方案：在第一和第二MOS晶体管两者的情况下（T1 = VC和I1 = VC）的情况下，第一MOS晶体管的栅极和源极之间的电压从第二MOS晶体管的栅极和源极之间的电压变为极性，在第一MOS晶体管导通的情况下第一MOS晶体管的栅极和源极以及在第二MOS晶体管从截止状态变为导通之后第一MOS晶体管从截止状态变为导通状态。版权所有（C）2005，JPO＆NCIPI

23. 发明专利

JP2004259362A Semiconductor memory 审中-公开
公开(公告)号：JP2004259362A
公开(公告)日：2004-09-16
申请号：JP2003048481
申请日：2003-02-26
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KOTABE AKIRA , OSADA KENICHI , SAITO YOSHIKAZU , KAWAHARA TAKAYUKI , YAMAOKA MASANAO
IPC分类号： G11C11/413 , G11C11/41
摘要： PROBLEM TO BE SOLVED: To solve the problem that when thresholds of switches for cutting power source of memory peripheral circuits and memory cells are made higher than that of transistors constituting the memory peripheral circuits in order to lower the leakage of a semiconductor memory, circuit performance is deteriorated by low voltage.
SOLUTION: A semiconductor memory has a plurality of static type memory cells, a circuit (memory peripheral circuit) which controls the memory cells and to which the operation voltage smaller than that of the memory cells is applied and MOSFETs which are connected between the memory peripheral circuit and wiring which supplies the voltage of the lower one of the operation voltages of the memory peripheral circuit. In the semiconductor memory, when the memory peripheral circuit is operated, the same voltage as the operation voltage of the memory cells is applied to the gates of the MOSFETs. Thus, the driving force of the MOSFETs can be made large even at the low voltage and the lowering of the leakage of the memory is attained while maintaining the performance of memory arrays and the memory peripheral circuits.
COPYRIGHT: (C)2004,JPO&NCIPI

24. 发明专利

JP2004054473A Memory card, information apparatus and information distribution method 审中-公开
公开(公告)号：JP2004054473A
公开(公告)日：2004-02-19
申请号：JP2002209339
申请日：2002-07-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HIRANO YASUHIRO , OTA MASUTOMI , HATAE HIROSHI , KAWAHARA TAKAYUKI , OSABE TARO , SAKAMOTO KOJI
IPC分类号： G06F12/14 , G06K17/00 , G06K19/00 , G06K19/073
摘要： PROBLEM TO BE SOLVED: To provide a memory card with a use limiting function capable of easily setting a user, a use apparatus, use conditions or the like, and to provide a device and a method applied therewith. SOLUTION: In the memory card 1 with a copyright protecting function incorporated with a controller LSI, a secure area 101 and a semi-secure area 102 are configured to store data for copyright protection such as key data or license data, and used as an area inaccessible with a command. On the other hand, a standard memory area 103 is used as an area accessible with a command, and encrypted contents or non-secure data are stored in a conventional memory card. This invention is configured by newly adding a use condition setting area part 104 in which use limit information is registered. An permitted user is limited to the reading of the data stored in the use condition setting area 104. COPYRIGHT: (C)2004,JPO

25. 发明专利

JP2007128645A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2007128645A
公开(公告)日：2007-05-24
申请号：JP2006338452
申请日：2006-12-15
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , SATO HIROSHI , NOZOE ATSUSHI , YOSHIDA KEIICHI , NODA TOSHIFUMI , KUBONO SHOJI , KOTANI HIROAKI , KIMURA KATSUTAKA
IPC分类号： G11C16/02 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To increase the speed of writing operation to a non-volatile memory cell. SOLUTION: The semiconductor integrated circuit is provided with a plurality of non-volatile memory cells to which electric erasure and writing are made possible and includes a control means for applying a pulse-shaped voltage to the non-volatile memory cell until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed into a second threshold voltage. At this time, the control means controls the second threshold voltage into a voltage lower than a power source voltage and having a range equal to or wider than a half range of the power source voltage. Thereby, the semiconductor integrated circuit can have only coarse writing as a writing mode. Since the number of pulses required for changing the threshold voltage of the memory cell is lower in the coarse writing mode, writing operation speed is increased. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提高写入操作到非易失性存储单元的速度。解决方案：半导体集成电路设置有多个非易失性存储单元，电子擦除和写入成为可能，并且包括用于向非易失性存储单元施加脉冲形电压的控制装置，直到具有第一阈值电压的非易失性存储单元的阈值电压被改变为第二阈值电压。此时，控制装置将第二阈值电压控制为低于电源电压并具有等于或大于电源电压的一半范围的范围的电压。因此，半导体集成电路可以仅具有粗写作为写入模式。由于在粗写模式下，改变存储单元的阈值电压所需的脉冲数较少，所以写操作速度增加。版权所有（C）2007，JPO＆INPIT

26. 发明专利

JP2006190380A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006190380A
公开(公告)日：2006-07-20
申请号：JP2005000863
申请日：2005-01-05
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： OSADA KENICHI , KAWAHARA TAKAYUKI
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C5/147 , G11C8/08 , G11C13/0028 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To improve the reliability of the phase change elements by eliminating unnecessary currents in the elements. SOLUTION: This semiconductor device has a memory cell to store information by changing its state with the temperature changes applied and an input and output circuits. It holds the word lines off until the power supply circuit starts right after the power supply is turned on. Accordingly, unnecessary currents do not flow in the elements, and the data can be prevented from being destroyed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过消除元件中的不必要的电流来提高相变元件的可靠性。解决方案：该半导体器件具有通过随着温度变化而改变其状态以及输入和输出电路来存储信息的存储单元。在电源打开后，电源电路立即开始关闭字线。因此，不必要的电流不会流入元件，并且可以防止数据被破坏。版权所有（C）2006，JPO＆NCIPI

27. 发明专利

JP2006004974A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2006004974A
公开(公告)日：2006-01-05
申请号：JP2004176669
申请日：2004-06-15
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAOKA MASANAO , OSADA KENICHI , ITO KIYOO , KAWAHARA TAKAYUKI
IPC分类号： H01L27/11 , G11C11/00 , G11C11/412 , H01L21/8242 , H01L21/8244 , H01L27/108 , H01L29/786
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/108 , H01L27/1203 , Y10S257/903
摘要： PROBLEM TO BE SOLVED: To improve performance of a memory cell by constituting an SRAM memory cell with an FD-SOI transistor and then controlling a potential of the lower layer of the embedded oxide film of the SOI transistor to form a drive transistor, and to improve performance of the SRAM circuit under the low power supply voltage condition.
SOLUTION: In the SRAM memory cell constituted by using an FD-SOI transistor, stable operation of the memory cell is realized by increasing a well potential under the BOX layer of the drive transistor in order to control the Vth.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过构成具有FD-SOI晶体管的SRAM存储单元，然后控制SOI晶体管的嵌入氧化膜的下层的电位来形成驱动晶体管来提高存储单元的性能并且在低电源电压条件下提高SRAM电路的性能。解决方案：在通过使用FD-SOI晶体管构成的SRAM存储单元中，通过增加驱动晶体管的BOX层下的阱电位来实现存储单元的稳定操作，以便控制Vth。版权所有（C）2006，JPO＆NCIPI

28. 发明专利

JP2005244247A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005244247A
公开(公告)日：2005-09-08
申请号：JP2005082073
申请日：2005-03-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , MATSUZAKI NOZOMI , SAWASE TERUMI , KUBO SEIJI
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To restrict the variable control of a logic with respect to a variable logic unit. SOLUTION: A semiconductor device mounted with a non-volatile memory unit (8) and the variable logic unit (3) has a non-volatile memory unit (8) having a rewritable non-volatile memory cell, the variable logic unit (3) of which the logic function can be decided in accordance with logical configuration definition data loaded into a plurality of memory cells, and a write-enable circuit (53). The write-enable circuit restricts the writing of the logical configuration definition data supplied from the outside of the semiconductor device, and for example, permits writing only when a password is supplied. When each of a vendor side and a user side implements a program for the variable logic unit, the vendor side can impose restrictions on the writing by specifying the user. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：限制相对于可变逻辑单元的逻辑的可变控制。解决方案：安装有非易失性存储器单元（8）和可变逻辑单元（3）的半导体器件具有具有可重写非易失性存储单元的非易失性存储单元（8），可变逻辑单元（3），其逻辑功能可以根据加载到多个存储单元中的逻辑配置定义数据和写使能电路（53）来确定。写使能电路限制从半导体器件的外部提供的逻辑配置定义数据的写入，并且例如仅在提供密码时才允许写入。当供应商侧和用户侧的每个实现可变逻辑单元的程序时，供方侧可以通过指定用户来对写入施加限制。版权所有（C）2005，JPO＆NCIPI

29. 发明专利

JP2005102281A Semiconductor circuit 有权
标题翻译：半导体电路
公开(公告)号：JP2005102281A
公开(公告)日：2005-04-14
申请号：JP2004323953
申请日：2004-11-08
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HORIGUCHI SHINJI , UCHIYAMA KUNIO , ITO KIYOO , SAKATA TAKESHI , AOKI MASAKAZU , KAWAHARA TAKAYUKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that realizes high speed / low power consumption even when an MOS transistor is microfabricated, and to realize a low-voltage-operable electronic apparatus, such as a battery-driven type, with low current consumption. SOLUTION: Between a source of the MOS transistor and a power source, a control circuit means is inserted to control current supply of large current and small current and these currents are switched in response to a use and supplied to the MOS transistor. For example, when a high-speed operation is requested, the large current is supplied and when low power consumption is requested, the small current is supplied. A logic circuit LC wherein a sub-threshold current is allowed to flow in a stand-by status, is connected through a switch to a high-level power source VHH and a low-level power source VLL. A level hold circuit LH is connected to an output terminal OUT of the logic circuit LC. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使在MOS晶体管被微制造的情况下，提供即使实现高速/低功耗的半导体集成电路，并且为了实现诸如电池驱动型的低电压可操作的电子设备，具有低电流消耗。解决方案：在MOS晶体管的源极和电源之间插入控制电路装置以控制大电流和小电流的电流供应，并且这些电流响应于使用被切换并被提供给MOS晶体管。例如，当要求高速运行时，提供大电流，并且当要求低功耗时，提供小电流。允许亚阈值电流在备用状态下流动的逻辑电路LC通过开关连接到高电平电源VHH和低电平电源VLL。电平保持电路LH连接到逻辑电路LC的输出端子OUT。版权所有（C）2005，JPO＆NCIPI

30. 发明专利

JP2004207694A Semiconductor device 有权
公开(公告)号：JP2004207694A
公开(公告)日：2004-07-22
申请号：JP2003381083
申请日：2003-11-11
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： OSADA KENICHI , YAMAOKA MASANAO , KAWAHARA TAKAYUKI
IPC分类号： H01L21/762 , G11C11/412 , H01L21/336 , H01L21/76 , H01L21/8238 , H01L21/8244 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/12 , H01L29/49 , H01L29/786
CPC分类号： H01L29/78648 , G11C11/412 , H01L21/823878 , H01L21/84 , H01L27/0928 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/4908 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an MISFET of a threshold requested for the operation of a circuit in a semiconductor device using an SOI substrate. SOLUTION: A gate electrode of a P-channel MISFET constituting a memory cell is formed by N type polysilicon and a gate electrode of an N-channel MISFET is formed by P type polysilicon. Gate electrodes of the P-channel MISFET and the N-channel MISFET of a peripheral circuit and a logic circuit are formed by P type silicon germanium. Consequently, an optimum threshold is obtained in each circuit by using an SOI substrate and the characteristics of the SOI substrate is fully utilized. COPYRIGHT: (C)2004,JPO&NCIPI

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