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21. 发明专利

JPS5138839A 失效
公开(公告)号：JPS5138839A
公开(公告)日：1976-03-31
申请号：JP11192774
申请日：1974-09-28
申请人： HITACHI LTD
发明人： KURAHASHI HIDEAKI , KATO MASAO , SUMIMOTO TSUTOMU
IPC分类号： G06F12/08 , G06F12/04 , G06F13/00 , G06F15/16

22. 发明专利

JPS5118440A 失效
公开(公告)号：JPS5118440A
公开(公告)日：1976-02-14
申请号：JP8987974
申请日：1974-08-07
申请人： HITACHI LTD
发明人： KATO MASAO , SUMIMOTO TSUTOMU
IPC分类号： G06F9/22 , G06F9/06 , G06F9/30

23. 发明专利

JPH0514288B2 失效
公开(公告)号：JPH0514288B2
公开(公告)日：1993-02-24
申请号：JP21716885
申请日：1985-09-30
申请人： HITACHI LTD
发明人： SUMIMOTO TSUTOMU , TAKEUCHI HIDENORI
IPC分类号： G06F12/08 , G06F9/38

24. 发明专利

JPH03190159A SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH LOGIC 失效
公开(公告)号：JPH03190159A
公开(公告)日：1991-08-20
申请号：JP32919289
申请日：1989-12-19
申请人： HITACHI LTD
发明人： MIYAOKA SHUICHI , ODAKA MASANORI , SAWAMOTO HIDEO , KATO MASAO , SUMIMOTO TSUTOMU
IPC分类号： H01L27/118 , G11C11/401 , H01L21/82 , H01L27/10
摘要： PURPOSE:To enable the formation of a memory of large capacity and a large scale logic on the same chip without decreasing it in operation speed and increasing it in power consumption by a method where a memory section is formed of a CMOS memory cell or a high resistance load type NMOS memory cell, and a gate array section is formed of a Bi-CMOS logic gate composed of a bipolar transistor and a CMOS circuit. CONSTITUTION:An input latch circuit 24 out of the circuits of a memory section is formed of a CMOS circuit to be decreased in power consumption, and an X decoder 22, a Y decoder 23, and a sense amplifier & output circuit 25 are formed of a Bi-CMOS circuit to be lessened in power consumption and improved in operation speed. Readout data are inputted into a gate array section through the intermediary of an aligner circuit 27. The aligner circuit 27 is given as a dedicated logic circuit designed using a Bi-CMOS gate so as to lessen a semiconductor memory device in area keeping it high operation speed. As a clock amplifier 28 can be used in common for memory mats vertically adjacent to each other, two pairs of vertically arranged memory mats are symmetrically laid out, and the aligner circuit 27 and a clock amplifier 28 are arranged at a position shown by a dot-dash line A.

25. 发明专利

JPS62196730A STAGE CONTROL SYSTEM FOR DATA PROCESSOR 失效
公开(公告)号：JPS62196730A
公开(公告)日：1987-08-31
申请号：JP3947586
申请日：1986-02-25
申请人： HITACHI LTD
发明人： TAKEUCHI HIDENORI , SUMIMOTO TSUTOMU
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
摘要： PURPOSE:To make it unnecessary to provide a buffer register, etc., and also, to decrease the number of instruction processing cycles, by executing synchronously an operation between plural control parts. CONSTITUTION:A start routine is executed by cycles S2, S3 extending from the MXSTART signal of a cycle S1 to the MXSTOP signal of the cycle S3. By the IXSTART signal of the cycle S2, an instruction execution control stage signal IXEA is started, and instruction read-out Ai, Li are executed by the cycles S3, S4. In this case, when the instruction cannot be obtained immediately due to a fact that the instruction does not exist in the buffer memory of a memory access control part 32, etc., the instruction execution control stage becomes 'queuing state' in cycles S5-S7 by the IXWAIT signal, and in this case, the IXWAIT signal is turned on. When read-out of the instruction is ended, the IXWAIT signal is turned off in the cycle S7, an IXEA signal is turned on again, and the decoding (D) of the instruction of an instruction execution control part 31, and the read-out (A, L) of an operand are executed in cycles S8-S10.

26. 发明专利

JPS60229153A CONSTITUTION CONTROL SYSTEM OF COMPUTER SYSTEM 失效
公开(公告)号：JPS60229153A
公开(公告)日：1985-11-14
申请号：JP8438784
申请日：1984-04-26
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： TAJIRI KAZUO , INOUE MASANOBU , SUMIMOTO TSUTOMU , IKEDA HITOSHI
IPC分类号： G06F12/16 , G06F12/06
摘要： PURPOSE:To prevent program control from complexity due to the difference in memory constitution by dividing plural memory devices into plural sets and previously preparing plural modes for the combination of address numbers to be assigned to respective constitutional units. CONSTITUTION:Four constitutional units consisting of machine numbers 0-3 are prepared in a memory device MEM5 and four constitutional units consisting of machine numbers 8-11 are prepared in a memory device MEM6. If a single computer system is to be constituted by all devices shown in a Fig., a service processor SVP9 connects memory devices MCUs 7, 8, CPUs 1, 2, data transfer devices DCHs 3, 4, and the MEMs 5, 6 respectively to initialize the system. To obtain a continuous real address space, address numbers 0-7 are assigned to eight machine Nos. in the MEMs 5, 6. Therefore, the SVP9 selects one mode out of four address number assigning modes to assign the address number. If independent processing is started due to a trouble or the like, it is necessary to stop the use of respective devices, but the specification of an address number may be stopped in the MEM6.

27. 发明专利

JPS59119595A Logical lsi incorporating ram 失效
标题翻译： LOGIC LSI INCORPORATING RAM
公开(公告)号：JPS59119595A
公开(公告)日：1984-07-10
申请号：JP22684482
申请日：1982-12-27
申请人： Hitachi Ltd
发明人： SUMIMOTO TSUTOMU , ISHIYAMA AKIRA , KAMIJIYOU YOSHIO
IPC分类号： G11C29/00 , G01R31/28 , G11C29/02 , G11C29/08 , G11C29/56
CPC分类号： G11C29/08
摘要： PURPOSE:To take an excellent test by transferring test data set in a write register and writing it in an RAM by the same clock when an RAM test mode is specified externally, and outputting the contents of the RAM read out to a read register by the same clock. CONSTITUTION:The basic pattern of write data from a data pin 20 to the RAM is set in a register 4 in normal mode and then a test mode is set to supply microinstructions, one after another, from a pin 23, taking a test of the RAM. Output data outputted from the RAM2 to the data pin 20 by four bytes at a time is compared with an expected value to test whether the RAM is normal or not. Thus, the test mode is provided and data pins of an LSI correspond to read/ write registers in the RAM, one to one, in said test mode; and data is inputted and outputted by using a clock in normal mode, so the influence of variance in signal delay time among peripheral logical circuits is reduced greatly to take the severse RAM test easily.
摘要翻译：目的：通过将写入寄存器中的测试数据设置为转移，并在外部指定RAM测试模式时以相同的时钟将其写入RAM，通过传输测试数据进行优异的测试，并将读出的RAM的内容输出到读取寄存器同一时钟构成：从数据引脚20到RAM的写入数据的基本模式在正常模式下设置在寄存器4中，然后设置测试模式，以从引脚23一个接一个地提供微指令，并对其进行测试随机存取存储器。将一次从RAM2输出到数据引脚20的四个字节的输出数据与预期值进行比较，以测试RAM是否正常。因此，在所述测试模式下，提供测试模式并且LSI的数据引脚对应于RAM中的读/写寄存器，一对一; 并且通过使用正常模式的时钟来输入和输出数据，所以在外围逻辑电路中的信号延迟时间的变化的影响被大大降低以便容易地进行反向RAM测试。

28. 发明专利

JPS5895855A DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5895855A
公开(公告)日：1983-06-07
申请号：JP19345281
申请日：1981-12-01
申请人： HITACHI LTD
发明人： SUMIMOTO TSUTOMU , KATOU MASAO , MINAMI HIDEKAZU
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118
摘要： PURPOSE:To make the size of a semiconductor chip small, and to improve the degree of integration by ameliorating the utilization efficiency of the area of the chip. CONSTITUTION:Blocks 14 are arranged into the internal area 13 of the semiconductor chip in the (x) direction, and these block rows are disposed only by rows required in the (y) direction. The nearer the positions of the blocks to a central section are, the smaller the size YB in the (y) direction of each block 14 is made, and the nearer the positions of the blocks to the central section of the chip are, the wider the intervals LX (space for wiring among the blocks in the (x) direction) of the block rows are made and the nearer the positions of the blocks to peripheral sections are, the narrower the intervals are made. The size YB of the blocks 14 is determined so that intervals LX at the positions correspond to the density of wiring among the blocks in the (x) direction at the positions. Consequently, the generation of wasteful space can be prevented while space for wiring among the blocks required is ensured among the block rows because the size in the (y) direction of each block is changed in consideration of the density of wiring at the positions of the blocks. Accordingly, the internal area of the semiconductor chip can be utilized efficiently as compared to conventional devices, and equal functions can be integrated onto the small semiconductor chip.

29. 发明专利

JPS5825299B2 失效
公开(公告)号：JPS5825299B2
公开(公告)日：1983-05-26
申请号：JP844776
申请日：1976-01-30
申请人： HITACHI LTD
发明人： SUMIMOTO TSUTOMU , KATO MASAO
IPC分类号： G06F12/00 , G11C7/22

30. 发明专利

JPS5622152A MEMORY ACCESS SYSTEM 失效
公开(公告)号：JPS5622152A
公开(公告)日：1981-03-02
申请号：JP9759079
申请日：1979-07-31
申请人： HITACHI LTD
发明人： TAKEUCHI HIDENORI , IKEDA KOUICHI , KATOU MASAO , SUMIMOTO TSUTOMU
IPC分类号： G06F9/38 , G06F9/30 , G06F12/06 , G06F13/00
摘要： PURPOSE:To realize the preceding reading of the instruction without giving any effect to the instruction under execution, by delivering the preceding read request of the instruction to the next bank different from the request bank in case the read request of the operand is given while the preceding instruction is being excuted. CONSTITUTION:CPU1 reads the instructions one by one which are stored in main memory device MS2 out of instruction control part CO14 and then decodes them to transfer them to execution control part EC15. Thus the instruction is executed at EC15. With this action, the execution is prepared for the next instruction at CO14 and during the execution period of the preceding instruction. Starting from the read request of the operand, the execution of the next instruction is prepared duing the execution of the preceding instruction. And the preceding read request of the instruction is delivered to the bank different from the bank of the instruction under execution among banks 26-29 storing the data. In such way, the preceding reading is possible for the instruction in duplication to the operand reading period, thus reducing the time to execute the instruction.

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