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1. 发明专利

JPS6079438A SYSTEM SWITCHING CONTROL SYSTEM OF INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS6079438A
公开(公告)日：1985-05-07
申请号：JP18821683
申请日：1983-10-07
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD
发明人： ISHIKAWA AKIHIKO , TAJIMA SEIJIROU , SUMIMOTO TSUTOMU , FUJIHIRA YASUO
IPC分类号： H04Q3/545 , G06F11/20
摘要： PURPOSE:To perform system switching operation in safety by allowing one processing system to send out an interruption signal to an other processing system on detecting its trouble, and allowing the other processing system to send out a stop signal for instruction executing operation to the former system and then carry on the processing. CONSTITUTION:An in-use system 1 and a stand-by system 51 consists of CPUs 2 and 53, monitoring devices 6 and 56, etc., and share a switching device 102, input/output equipment 103-108, etc. If a fault occurs in the device 6 firstly, an interruption for the internal machine check on the CPU2 is initiated and an interruption to the device 56 is caused; and the CPU2 stops after executing an instruction instantaneously or only a prescribed instruction, and the CPU52 on receiving the interruption of the device 56 executes a forcible indication instruction and then switches systems through the device 102 to connect equipments 103-108 to the stand-by system, thereby restarting the business. Consequently, the safety of the switching operation between the systems is securely by adding small hardware.

2. 发明专利

JPS55163698A MEMORY PROTECTING SYSTEM 失效
公开(公告)号：JPS55163698A
公开(公告)日：1980-12-19
申请号：JP7098579
申请日：1979-06-06
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD
发明人： YASUMI NAOAKI , SEIJI TAKAYUKI , SHIOKAWA SHIZUO , SUMIMOTO TSUTOMU , OOKAWA MASAYUKI
IPC分类号： G06F12/14 , G06F12/08 , G06F12/10 , G06F13/00 , G11C29/00
摘要： PURPOSE:To simplify the memory protecting mechanism by using in common the memory protecting systems of both the real and logic address systems. CONSTITUTION:Logic address LA or real address RA is stored in address register AR10. The RA or LA system is designated according to the logic state of output 104 of program state word 5. Based on this designation, switch circuit 12 selects the contents of expanded real segment NO.9 or AR10. Adder 17 performs the calculation which is necessary for the converting process from LA to RA, and the result of calculation is applied to register 18. The comparison 15 is given between the segment No. comprising AR10 and circuit 12 and the segment No. of one item of address converting buffer 13 designated by decoder 14. With the coincidence signal 102, control circuit 20 gives the control to the converting process from LA to RA. Ring protecting circuit 16 examines the ring protecting conditions based on buffer 13 and output 103 of word 5 and then delivers memory protecting exception signal 101.

3. 发明专利

JPS60229153A CONSTITUTION CONTROL SYSTEM OF COMPUTER SYSTEM 失效
公开(公告)号：JPS60229153A
公开(公告)日：1985-11-14
申请号：JP8438784
申请日：1984-04-26
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： TAJIRI KAZUO , INOUE MASANOBU , SUMIMOTO TSUTOMU , IKEDA HITOSHI
IPC分类号： G06F12/16 , G06F12/06
摘要： PURPOSE:To prevent program control from complexity due to the difference in memory constitution by dividing plural memory devices into plural sets and previously preparing plural modes for the combination of address numbers to be assigned to respective constitutional units. CONSTITUTION:Four constitutional units consisting of machine numbers 0-3 are prepared in a memory device MEM5 and four constitutional units consisting of machine numbers 8-11 are prepared in a memory device MEM6. If a single computer system is to be constituted by all devices shown in a Fig., a service processor SVP9 connects memory devices MCUs 7, 8, CPUs 1, 2, data transfer devices DCHs 3, 4, and the MEMs 5, 6 respectively to initialize the system. To obtain a continuous real address space, address numbers 0-7 are assigned to eight machine Nos. in the MEMs 5, 6. Therefore, the SVP9 selects one mode out of four address number assigning modes to assign the address number. If independent processing is started due to a trouble or the like, it is necessary to stop the use of respective devices, but the specification of an address number may be stopped in the MEM6.

4. 发明专利

JPS5580872A MICROPROGRAM LOADING SYSTEM 失效
公开(公告)号：JPS5580872A
公开(公告)日：1980-06-18
申请号：JP15328578
申请日：1978-12-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： WATANABE NOBUYUKI , TAJIMA SEIJIROU , HAYAMIZU HARUO , YASUMI NAOAKI , SUMIMOTO TSUTOMU
IPC分类号： G06F9/22 , G06F12/08
摘要： PURPOSE:To prevent the mistaken alteration for the region proper to the hardware of the control memory by inhibiting the writing of the contents of the main memory into the control memory in case the address to load the contents of the main memory into the control memory is outside the designation region. CONSTITUTION:An access is given to the address which is designated by effective address register 19 in accordance with the contents of program counter 17, and then the order is read out of main memory 1. The contents of register 16 designated by part of the order read out is used as the writing address to control memory 2 and then applied to comparator 11 via operand register 13 to be then compared with the set value of lower and upper limit region registers 9 and 10 of firm region 4 which is to be rewritten in accordance with the program of memory 2 to be applied to comparator 11. And in case the writing address is outside the firm region range, the writing is inhibited for the data given to memory 2 from memory 1 by the inhibition signal delivered from comparator 11. As a result, the alteration due to the mistaken program can be prevented for region 3 proer to the hardware of memory 2.

5. 发明专利

JPS60140438A SYSTEM SWITCHING CONTROL SYSTEM OF INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS60140438A
公开(公告)日：1985-07-25
申请号：JP25221283
申请日：1983-12-27
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD
发明人： ISHIKAWA AKIHIKO , TAJIMA SEIJIROU , SUMIMOTO TSUTOMU , FUJIHIRA YASUO
IPC分类号： H04Q3/545 , G06F11/20 , G06F15/16 , G06F15/177
摘要： PURPOSE:To quarantee easily the operation of system switching by providing a signal transmitting means for transmitting an interruption to the 2nd processing system in response to the error detection in the 1st processing system in the information processing system comprising the 1st and the 2nd processing systems. CONSTITUTION:An SVP interruption signal line 111, a forced stop signal line 113 and an interruption reception signal line 115 from the active system 1 and an SVP interruption signal line 112, a forced stop signal line 114 and an interruption reception signal line 116 from the standby system 51 are connected respectively to the other system. When the CPU or the SVP is faulty in the active system, an SVP interruption generating circuit 225 generates an output signal. Moreover, in case of all software errors, an SVP interruption signal is transmitted to the stand-by system via the line 111. On the other hand, in case of the stand-by system, when the SVP interruption is generated via the signal line 112, it is stored in a storage circuit 201, an interruption reception signal is transmitted to the active system and the interruption is informed to the software by an interruption generation circuit 205.

6. 发明专利

JPS59217298A Memory error relieve system 失效
标题翻译：存储器错误信号系统
公开(公告)号：JPS59217298A
公开(公告)日：1984-12-07
申请号：JP9097883
申请日：1983-05-24
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： HIRANO MASANORI , OONO KUNIO , SUMIMOTO TSUTOMU , OZAKI HISAYASU
IPC分类号： G06F12/16 , G06F11/00 , G11C29/00
CPC分类号： G06F11/00
摘要： PURPOSE:To relieve a 1-bit memory error without providing any circuit which inhibits the memory access from other processor specially by employing a partial writing system, and reading 1-bit error data and rewriting corrected data in a single-time memory access. CONSTITUTION:A processor 16 sends a read request to a memory device 1 to which data 3 containing a 1-bit error is read out of a storage part 2 in the process of instruction execution, and sets the corresponding address in a memory address register 4, and the memory device 1 reads the data 3 out of the storage part 2 and inputs it to a humming check circuit 15 to detect the 1-bit error and correct the error bit. The processor 16 is informed of the 1-bit error from the memory device 1 through a signal line 9 in the instruction execution process, so the address of the 1-bit error data 3 is fetched from an error address register 5 through a bus 8 after the instruction execution is completed.
摘要翻译：目的：为了减轻1位存储器错误，而不提供任何电路，通过采用部分写入系统特别禁止其他处理器的存储器访问，并读取1位错误数据，并在单次存储器访问中重写修正后的数据。构成：在执行指令的过程中，处理器16将读取请求发送到存储装置1，在存储装置1中从包含1位错误的数据3读出存储部分2，并将相应的地址设置在存储器地址寄存器4中，并且存储装置1从存储部分2中读出数据3，并将其输入到蜂鸣检查电路15，以检测1位错误并纠正错误位。处理器16在指令执行过程中通过信号线9从存储器件1通知1位错误，因此1位错误数据3的地址通过总线8从错误地址寄存器5中提取指令执行完成后。

7. 发明专利

JPH0550017B2 失效
公开(公告)号：JPH0550017B2
公开(公告)日：1993-07-27
申请号：JP24548983
申请日：1983-12-28
申请人： HITACHI LTD
发明人： SUMIMOTO TSUTOMU , KATO MASAO
IPC分类号： G06F12/08 , G06F12/04
摘要： PURPOSE:To solve easily and surely a problem of destruction of a new data in a share memory due to a special full write by suppressing the special full write when a write address belongs to a block copied to a buffer memory so as to process it as a partial write. CONSTITUTION:A processing unit (CPU) 1 has a buffer memory 2 and its address registration directory (BAA) 3 and the access request to a main memory is processed all by an access request control section (RQCTL) 4. Another processing unit (IOP) 100 is provided with an access request control section 11. When a write request from the IOP100 enters an access request buffer N (RQBFB) 21, a write request is received by a reception control circuit (PRI) 30 and the write to a main memory (MS) 50 is conducted in the said address. An address registration directory (FAA) 40 being a copy of the BAA3 as to the address is referenced and when its address exists in the FAA40, the block registration is made ineffective and the registration of the said block in the BA3 is cancelled.

8. 发明专利

JPH0465547B2 失效
公开(公告)号：JPH0465547B2
公开(公告)日：1992-10-20
申请号：JP3327983
申请日：1983-03-01
申请人： HITACHI LTD
发明人： MINAMI HIDEKAZU , ARAI KYOKAZU , SUMIMOTO TSUTOMU , IKEDA KOICHI
IPC分类号： H01L21/822 , G06F5/06 , H01L21/60 , H01L21/82 , H01L27/04 , H01L27/118

9. 发明专利

JPH0157820B2 失效
公开(公告)号：JPH0157820B2
公开(公告)日：1989-12-07
申请号：JP6765484
申请日：1984-04-06
申请人： HITACHI LTD
发明人： KUMAGAI TAKASHI , SUMIMOTO TSUTOMU , TANIGUCHI TOSHIHISA
IPC分类号： G06F12/08
摘要： PURPOSE:To improve the through-out of a memory access of an input/output processing unit by checking an address in a block of access request to select whether the data is transferred in a form of block transfer or transferred directly from a main storage device to the input/output processing unit. CONSTITUTION:Suppose that a desired data does not exists in a buffer storage device (BS) 5 through the access from the input/output processing unit (IOP)2. When the 5th, 6th bits of an address register 3 are ''11'', a control circuit 6 starts a main storage device (MS) 7 so that a desired 16-byte data 34 only is transferred to the IOP2 through a data line 14. Regardless of above processing, the data is reduced to useless, since the 16-byte data 31-33 in the block are not fetched by this channel after the 16-byte data 34 is fetched even if a block 30 of the MS7 is transferred to the BS5. Thus, the direct transfer of the desired 16-byte data 34 only from the MS7 to the IOP2 has far less time.

10. 发明专利

JPH01270296A ELECTRONIC APPARATUS AND ITS COOLING METHOD 失效
公开(公告)号：JPH01270296A
公开(公告)日：1989-10-27
申请号：JP9813488
申请日：1988-04-22
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： KUMAGAI TAKASHI , OGURO TAKAHIRO , KATO MASAO , SUMIMOTO TSUTOMU , FURUNO SADAAKI
IPC分类号： H05K7/20 , H01L23/46 , H01L23/467
摘要： PURPOSE:To enable the cooling of semiconductor elements of large heating value, and realize the reduction of noise and the miniaturization of a cooling equipment, by air-cooling the semiconductor elements after the feeding air for the semiconductor elements is previously cooled. CONSTITUTION:As a cooling medium for an electronic apparatus provided with a plurality of semiconductor elements, air is used, which is previously cooled prior to the feeding of air to a semiconductor element circuit. As a result, high cooling capability is attained even by forced air-cooling, and semiconductor elements of large heating value can be effectively cooled. In the case where a refrigeration equipment is used as a cooling means of feeding air, a refrigeration cycle is repeated by a condenser 11, a compressor 14, an expansion valve 12 and an evaporator 13. The air fed to the electronic apparatus is cooled by the evaporator 13, and the semiconductor elements are cooled by said cooled air. Thereby, in the case of an electronic apparatus whose heating value is comparatively large, necessary cooling effect is attained, and the reduction of noise and the miniaturization of a cooling equipment can be realized.

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