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21. 发明专利

JPS61263239A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61263239A
公开(公告)日：1986-11-21
申请号：JP10372785
申请日：1985-05-17
申请人： HITACHI LTD
发明人： URAGAMI KEN , MATSUBARA TOSHIAKI , MAMIYOUDA HARUYOSHI , SUZUKI YASUNAGA
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118 , H03K19/173
摘要： PURPOSE:To obtain an IC having high integration at high speed with low power consumption by using as the basic cell of the IC a deformed 2-input cell having a signal input terminal in the cell and substantially equivalent function to 3-input cell. CONSTITUTION:An input buffer 20 has a level converting function for converting, for example, input signals INA, INB, INC of TTL level input from the exterior into signals of CMOS level, and inputting the output signal to a logic unit 31 formed of CMOS as a main unit. An output buffer 22 has a level converting function for converting, for example, a signal of the CMOS level into a signal of TTL level and eventually outputting, for example, an output signal OUT of TTL level. A basic cell for forming this circuit has apparently 2-input NAND to be used as a modified 2-input cell having substantially equivalent function to 3-input NAND in the circuit configuration by providing another signal input terminal in the cell.

22. 发明专利

JPS59130429A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59130429A
公开(公告)日：1984-07-27
申请号：JP24399183
申请日：1983-12-26
申请人： Hitachi Ltd
发明人： MATSUBARA TOSHIAKI
IPC分类号： H01L23/522 , H01L21/31 , H01L21/768
CPC分类号： H01L21/31
摘要： PURPOSE:To check the infiltration of contaminative ion by the groove and to prevent said ion from reaching an active region by separating a protective insulating film of a guide part from that of the active region by the groove and further by separating completely by a PSG flim formed thereon. CONSTITUTION:The protective insulating film is separated into two parts, regions 12a and 12b by an opening for contact arranged on an emitter region and the annular grooves 15. Among these, the protective film 12a present on the both sides is connected to an active region flatly whereas the internal protective film 12b is completely separated from the active region. When the emitter diffusion layer 11 is formed, a thin oxide film 12' is formed on the surface of said layer 11 and an opening B for contact and the grooves 15 for isolated regions are simultaneously formed after then. When the overall removal is finished leaving an aluminum wiring layer 13, an window 20 is produced, after which a PSG film 14 is formed on the whole surface.
摘要翻译：目的：检查凹槽中污染离子的渗透，并通过将槽引导部分的保护绝缘膜与有源区的保护绝缘膜分开，并通过PSG膜完全分离，防止所述离子到达有源区形成在其上。构成：保护绝缘膜通过布置在发射极区域上的接触开口和环形槽15分成两部分区域12a和12b。其中，存在于两侧的保护膜12a连接到有源区域内部保护膜12b与活性区域完全分离。当形成发射极扩散层11时，在所述层11的表面上形成薄氧化物膜12'和用于接触的开口B.此后，同时形成用于隔离区域的槽15。当总体去除完成留下铝布线层13时，产生窗口20，之后在整个表面上形成PSG膜14。

23. 发明专利

JPS5870562A PREPARATION OF LEAD FRAME 失效
公开(公告)号：JPS5870562A
公开(公告)日：1983-04-27
申请号：JP13408981
申请日：1981-08-28
申请人： HITACHI LTD
发明人： SHIMIZU KAZUO , MATSUBARA TOSHIAKI
IPC分类号： H01L23/50 , H01L23/495
摘要： PURPOSE:To flatten the surface by punching a lead frame, forming a V-groove of which both ends reach the side edge of tab lead at the surface of periphery of the line junction region of said tab lead and then by pressing said line contact region. CONSTITUTION:A V-groove 15 is provided in both sides of line contact region 12 of tab lead 4 in the width direction by the coining method. The region 12 between a pair of V-groove is partially pressed by the coining and thereby the flattened surface 13 can be formed. Deformation of mother material is prevented by specifying depth of V-groove and the coining. The region is formed like a mound by the coining in the side of V-groove 15. At this time, roundness of tab lead surface generated when the lead frame is formed is also eliminated and accurate and highly reliable line contact can be realized.

24. 发明专利

JPS5850772A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5850772A
公开(公告)日：1983-03-25
申请号：JP14789281
申请日：1981-09-21
申请人： HITACHI LTD
发明人： MATSUBARA TOSHIAKI
IPC分类号： H01L21/8224 , H01L21/331 , H01L27/082 , H01L29/68 , H01L29/73 , H01L29/78
摘要： PURPOSE:To obtain a lateral transistor available for the free trimming of the control of amplification factors and emitter dimensions, by controlling emitter currents by voltage impression onto a gate electrode. CONSTITUTION:Since a P type inversed layer 5 is generated on the surface of an N type Si substrate 1 under the gate by impressing a voltage onto the gate G and the area of a P type emitter 3 increases resulting in the reduction of a substantial base width WB, and thereby the amplification factor hFE of the lateral P-N-P transistor fluctuates by the gate voltage VG. Further, a plurality of P type emitters 3a, 3b are provided on the surface of an N layer 9, the gate G is provided on the surface of the N layer (base) between emitters via insulating films 4, the emitter area (peripheral length) is substantially increased by the P type inverted layer 5 generated by impressing a negative voltage onto the gate, and emitter currents are varied resulting in the fluctuation of the hFE. Thus, by providing an insulating gate electrode on the base and impressing a voltage thereon, the base width is varied resulting in the control of the hFE, and the N layer is formed on the base surface resulting in the control of the hFE. Further, collector currents are varied by making the emitter area and the peripheral length variable, and thereby programmable elements or elements available for trimming can be obtained.

25. 发明专利

JPS5391679A SEMICONDUCTOR HIGH BREAKDOWN VOLTAGE AND HIGH RESISTANCE ELEMENT 失效
公开(公告)号：JPS5391679A
公开(公告)日：1978-08-11
申请号：JP594077
申请日：1977-01-24
申请人： HITACHI LTD
发明人： MATSUBARA TOSHIAKI
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L27/06 , H01L29/08 , H01L29/73
摘要： PURPOSE:To manufacture high breakdown voltage and high resistance element, by forming the emitter layer split by N into the base layer without contacting the substrate and the epitaxial layer and by selecting the breakodown voltage VR and the base-to-emitter breakdown voltage BVEBO in target as the specified relation.

26. 发明专利

JP2510018B2 失效
公开(公告)号：JP2510018B2
公开(公告)日：1996-06-26
申请号：JP1601190
申请日：1990-01-29
申请人： HITACHI LTD
发明人： SUZUKI YUKIRO , MASUDA IKURO , IWAMURA MASAHIRO , KATONO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118 , H03K19/0175

27. 发明专利

JPS61193467A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61193467A
公开(公告)日：1986-08-27
申请号：JP3269285
申请日：1985-02-22
申请人： HITACHI LTD
发明人： NISHIO YOJI , MATSUBARA TOSHIAKI , FURUTOKU SHOICHI , MURABAYASHI FUMIO
IPC分类号： H01L21/82 , H01L27/118
摘要： PURPOSE:To increase the efficiency of packaging of mounted gates by a construction wherein the width of chip central reinforcement lines is multiplied integrally as against basic cells and made allowable for the density of a current flowing therethrough, and further basic cells are formed also under the chip reinforcement lines. CONSTITUTION:A chip central power reinforcement line 10 formed of Al 2 runs in the logitudinal direction and is connected to power lines 22 on basic cells through a through hole and also to a chip peripheral power line 23. A chip central earthing power reinforcement line 11 formed of Al 2 runs likewise in the longitudinal direction and is connected to earthing power lines 26 on the basic cells through a through hole and also to a chip peripheral earthing power line 27 through the through hole and an Al 1 wiring 29. In this constitution, the width of the chip central reinforcement lines 10 and 11 is multiplied integrally as against that of the basic cells 20 and narrowed toward the central portion in accordance with the density of a current flowing therethrough. Accordingly, basic cells which can be developed as logic gates are increased in the place wherein the chip central reinforcement lines 10 and 11 are narrowed, and therefore the number of mounted gates can be increased in the same chip area in comparison with a gate array having a uniform width.

28. 发明专利

JPS59139725A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59139725A
公开(公告)日：1984-08-10
申请号：JP1271283
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： SUZUKI YUKIROU , MASUDA IKUROU , IWAMURA MASAHIRO , KATOUNO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H03K19/0185 , H03K19/0175 , H03K19/018 , H03K19/08 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09448 , H03K19/1778 , H03K19/17792
摘要： PURPOSE:To reduce both the delay time of transmission and the dependency on capacity for a semiconductor IC device by providing an input buffer for TTL- CMOS level conversion and an input buffer for CMOS-TTL level conversion and using a bipolar transistor to the output of a buffer converter. CONSTITUTION:A semiconductor IC device is provided with an input buffer 20 for TTL-CMOS conversion, an output buffer 22 for CMOS-TTL conversion and an internal logical block 21 which works at the CMOS level. The input signals IN1-IN19 of TTL levels are converted into CMOS levels by level converters 201-20n of the buffer 20. These converted signals of CMOS levels are applied to each logical gate of the block 21. Then bipolar output TRs Q1 and Q2 are used to charge or discharge the output capacity CS of each of converters 201-20n of the buffer 20. This device reduces both the delay time of transmission and the dependency on capacity and increases the working speed of the semiconductor IC device.
摘要翻译：目的：通过提供用于TTL-CMOS电平转换的输入缓冲器和用于CMOS-TTL电平转换的输入缓冲器以及使用双极晶体管来输出半导体IC器件的输出，以减少传输的延迟时间和半导体IC器件的容量依赖性一个缓冲转换器。构成：半导体IC器件具有用于TTL-CMOS转换的输入缓冲器20，用于CMOS-TTL转换的输出缓冲器22和工作于CMOS电平的内部逻辑块21。 TTL电平的输入信号IN1-IN19由缓冲器20的电平转换器201-20n转换成CMOS电平。这些CMOS电平的转换信号被加到块21的每个逻辑门。然后双极性输出TR Q1和Q2是用于对缓冲器20的每个转换器201-20n的输出电容CS进行充电或放电。该装置减小了传输的延迟时间和对容量的依赖性，并且增加了半导体IC器件的工作速度。

29. 发明专利

JPS59139724A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59139724A
公开(公告)日：1984-08-10
申请号：JP1271183
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： SUZUKI YUKIROU , MASUDA IKUROU , IWAMURA MASAHIRO , KATOUNO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H03K19/0185 , H03K19/0175 , H03K19/018 , H03K19/08 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09448 , H03K19/1778 , H03K19/17792
摘要： PURPOSE:To reduce the dependency on the output capacity for the working speed of a buffer and to improve the degree of integration by using an internal logical block which works at the CMOS level, a buffer for TTL-CMOS level input conversion and a buffer for CMOS-TTL level output conversion. CONSTITUTION:A semiconductor integrated circuit device is provided with an input buffer 20 for TTL-CMOS level conversion, an internal logical block 21 which works at the CMOS level and an output buffer 22 for CMOS-TTL level conversion. The input signals of TTL levels supplied to terminals 1-19 are converted into CMOS levels by input level converters 201-20n of the buffer 20 and then applied to each gate of a block 21. The output signal of CMOS level delivered from the block 21 is converted into the TTL level through each of level converters 221-22m of the buffer 22 and delivered. Each transistor TR of buffers 20 and 22 is converted into a bipolar TR. This device reduces the dependency on the output capacity for the buffer working speed and improves the density of integration.
摘要翻译：目的：为了减少对缓冲器工作速度的输出容量的依赖性，并通过使用工作于CMOS电平的内部逻辑块来提高积分程度，一个用于TTL-CMOS电平输入转换的缓冲器和一个用于 CMOS-TTL电平输出转换。构成：半导体集成电路器件具有用于TTL-CMOS电平转换的输入缓冲器20，工作于CMOS电平的内部逻辑块21和用于CMOS-TTL电平转换的输出缓冲器22。提供给端子1-19的TTL电平的输入信号由缓冲器20的输入电平转换器201-20n转换成CMOS电平，然后施加到块21的每个栅极。从块21传送的CMOS电平的输出信号通过缓冲器22的每个电平转换器221-22m被转换成TTL电平并传送。缓冲器20和22的每个晶体管TR被转换成双极性TR。该设备减少了对缓冲区工作速度的输出容量的依赖性，并提高了集成密度。

30. 发明专利

JPS58198908A Semiconductor device equipped with protecting circuit 失效
标题翻译：配有保护电路的半导体器件
公开(公告)号：JPS58198908A
公开(公告)日：1983-11-19
申请号：JP8143782
申请日：1982-05-17
申请人： Hitachi Ltd
发明人： MATSUBARA TOSHIAKI
IPC分类号： H03F1/42 , H03F1/52
CPC分类号： H03F1/52
摘要： PURPOSE:To increase the degree of integration and to prevent a surface breakdown between the emitter and base of a bipolar TR by forming a Zener diode structure between the 1st conduction type emitter area and the 2nd conduction type base area of the TR. CONSTITUTION:An epitaxial growth layer 3 is formed on a semiconductor substrate 1 and an island 10 is formed of an insulating layer 4. An N layer 8 as a collector C and a P layer 5 as a base B are formed in the island 10 and an N layer 7 as an emitter E is formed in a base B by impurity diffusion. Further, a P layer 6 is formed at part of the P layer 5 in contact with at least the bottom surface part of the N layer 7. In this case, the diameter B of the P layer is less than the diameter A of the N layer. Therefore, an area with higher dielectric strength than an original TR is formed at the contacting part between the P layer 6 and emitter layer 7, so a breakdown occurs to not the surface, but this contacting part.
摘要翻译：目的：通过在TR的第一导电型发射极区域和第二导电型基极区域之间形成齐纳二极管结构来增加积分度并防止双极性TR的发射极和基极之间的表面击穿。构成：外延生长层3形成在半导体衬底1上，岛10由绝缘层4形成。作为集电体C的N +层8和作为基底B的P层5形成在岛10和作为发射极E的N +层7通过杂质扩散形成在基底B中。此外，在P层5的至少与N +层7的底面部分接触的部分处形成P +层6.在这种情况下，P +层的直径B 小于N +层的直径A。因此，在P +层6和发射极层7之间的接触部分处形成具有比原始TR更高的介电强度的区域，因此不发生击穿而不是表面，而是接触部分。

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