专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH0542821B2 失效
公开(公告)号：JPH0542821B2
公开(公告)日：1993-06-29
申请号：JP16869781
申请日：1981-10-23
申请人： HITACHI LTD
发明人： KATONO SHINJI , FUJITA MINORU , MASUDA KOJI
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52 , H05K1/00

2. 发明专利

JPH02223221A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02223221A
公开(公告)日：1990-09-05
申请号：JP1601490
申请日：1990-01-29
申请人： HITACHI LTD
发明人： SUZUKI YUKIRO , MASUDA IKUO , IWAMURA MASAHIRO , KATONO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H03K19/0175 , G11C11/407
摘要： PURPOSE:To reduce a propagation delay time and its output capacitor dependency by comprising an output transistor to execute the charge and discharge of the output capacitor of an input/output level converter of a bipolar transistor. CONSTITUTION:The title device is equipped with an internal logic block 11 including a CMOS circuit and an input circuit 10 including the bipolar transistor to drive the input of the block. And a storage means is provided in the internal logic block 11. In the level converters of input and output buffers 10 and 12 for TTL-CMOS level conversion for the internal logic block 11 operated by a CMOS level, the output transistor which executes the charge or discharge of the level converter is comprised of the bipolar transistor. Thereby, the propagation delay time and the capacitor dependency of the input and output buffers 10 and 12 can be reduced.

3. 发明专利

JPH02223220A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02223220A
公开(公告)日：1990-09-05
申请号：JP1601390
申请日：1990-01-29
申请人： HITACHI LTD
发明人： SUZUKI YUKIRO , MASUDA IKURO , IWAMURA MASAHIRO , KATONO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H03K19/173 , H03K19/0175 , H03K19/08
摘要： PURPOSE:To reduce a propagation delay time and its output capacitor dependency by comprising an output transistor to execute the charge or discharge of the output capacitor of an input/output level converter of a bipolar transistor. CONSTITUTION:The title device is equipped with an internal logic block 11 having plural logic gate circuits including at least CMOS circuits and an input circuit 10 including the bipolar transistor to drive the input of the block. And the plural logic gate circuits are connected mutually with a gate array method. In the level converters of input and output buffers 10 and 12 for TTL-CMOS level conversion for the internal logic block 11 operated by a CMOS level, the output transistor which executes the charge and discharge of the output capacitor of the level converter is comprised of the bipolar transistor. Thereby, the propagation delay time and the capacitor dependency of the input and output buffers 10 and 12 can be reduced.

4. 发明专利

JPS6132621A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS6132621A
公开(公告)日：1986-02-15
申请号：JP15288684
申请日：1984-07-25
申请人： Hitachi Ltd
发明人： KATONO SHINJI , SUZUKI YUKIRO , NISHIO YOJI
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/173
摘要： PURPOSE: To speed up its operation greatly without increasing the total power consumption by classifying plural logical elements which constitute a unit cell into two kinds according to their circuit positions, and using a high load drive type gete as its output gate.
CONSTITUTION: A device IC is a gate array; an input buffer part 20 consists of input buffer circuits 201∼20n and an output buffer part 22 consists of output buffer circuits 221∼21n. High-load drive type gates are used as output gates (output buffers) which send out respective outputs L22 as to unit cells 211∼21n of an internal circuit part 21. Namely, high load driving ability circuits are used as output buffers of the unit cells to equalize signal delay almost to the signal delay between gates in unit cells regardless of whether the length of wiring connecting unit cells mutually. The occupation rate of the output buffers is small, so the whole power consumption does not increase greatly. Further, the operation of the gate array is speeded up and malfunction of the circuit due to variance in delay quantity is prevented.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过将构成单元的多个逻辑元件根据其电路位置分为两种，并使用高负载驱动型gete作为其输出门，来大大加快其运行，而不增加总功耗。构成：器件IC是门阵列; 输入缓冲器部分20由输入缓冲器电路201-20n组成，输出缓冲器部分22由输出缓冲器电路221-21n组成。高负载驱动型门用作输出门（输出缓冲器），其向内部电路部分21的单位单元211-21n发出相应的输出L22。即，高负载驱动能力电路用作单元的输出缓冲器单元以使信号延迟几乎与单元单元中的门之间的信号延迟相等，而不管互连单元单元的布线长度。输出缓冲器的占用率小，整体功耗不大。此外，门阵列的操作加速，并且防止由于延迟量的变化引起的电路故障。

5. 发明专利

JPS6019028B2 失效
公开(公告)号：JPS6019028B2
公开(公告)日：1985-05-14
申请号：JP10155377
申请日：1977-08-26
申请人： HITACHI LTD
发明人： ASANO MICHIO , IWAMOTO SHOJI , KATONO SHINJI , TSUJIOKA SHIGEO
IPC分类号： G06F9/22 , G06F9/28 , G06F9/38 , G06F15/16 , G06F17/16

6. 发明专利

JPH03217055A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03217055A
公开(公告)日：1991-09-24
申请号：JP1235390
申请日：1990-01-22
申请人： HITACHI LTD
发明人： KATONO SHINJI , SHIBATA MANABU , SAKAMOTO MASATAKA , KOMATSU TORU
IPC分类号： H01L21/8249 , H01L21/82 , H01L27/06 , H01L27/118
摘要： PURPOSE:To realize high speed operation while maintaining high integration by forming CMOS basic cells and Bi-CMOS basic cells in mixture, and forming a logic circuit where the Bi-CMOS and CMOS basic cells are used separately according to the magnitude of a load capacity. CONSTITUTION:As an inner logic circuit, CMOS basic cells and Bi-CMOS basic cells are formed in mixture. If its load capacity is relatively large, a specific logic circuit is formed of the Bi-CMOS basic cell, while if the capacity is relatively small, a specific logic circuit is formed of the CMOS basic cell. For example, as the basic cell for forming the inner logic circuit, a gate row of the Bi-CMOS basic cells is arranged in a first row, and a gate row of CMOS basic cells are arranged in second and third rows. The CMOS basic cells are disposed at a ratio of 2 to 1 of the Bi-CMOS basic cells similarly, for the fourth and following rows.

7. 发明专利

JPH02223219A ELECTRONIC SYSTEM 失效
公开(公告)号：JPH02223219A
公开(公告)日：1990-09-05
申请号：JP1601290
申请日：1990-01-29
申请人： HITACHI LTD
发明人： SUZUKI YUKIRO , MASUDA IKURO , IWAMURA MASAHIRO , KATONO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H03K19/0175
摘要： PURPOSE:To reduce propagation delay time and its output capacitor dependency by comprising an output transistor which executes the charge or discharge of the output capacitor of an input/output level converter of a bipolar transistor. CONSTITUTION:The title system is provided with an internal logic block 1 including at least a CMOS circuit and the output circuit 12 including the bipolar transistor which derives the output of the block to an external output lead. In the level converters of input and output buffers 10 and 12 for TTL-CMOS level conversion for an internal logic block 11 operated by a CMOS level, the output transistor which executes the charge and discharge of the output capacitor of the level converter is comprised of the bipolar transistor. The element dimension and the output resistance of the bipolar transistor are set less than a MOSFET, and the current amplification factor of it exceeds that of the MOSFET, therefore, a large charging current or discharging current can be obtained. Thereby, the propagation delay time and the capacitor dependency of the input and output buffers 10 and 12 can be reduced.

8. 发明专利

JPS61263318A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61263318A
公开(公告)日：1986-11-21
申请号：JP10372885
申请日：1985-05-17
申请人： HITACHI LTD
发明人： SHIBATA MANABU , URAGAMI KEN , KATONO SHINJI , SUZUKI YUKIRO
IPC分类号： H01L27/092 , H01L21/82 , H01L21/8238 , H01L27/118 , H03K19/0175 , H03K19/0944 , H03K19/173
摘要： PURPOSE:To expand the utilizing range of a gate array by providing an additional circuit element together with the circuit element of an inverter form as an input buffer section so as to expand the kind of an input buffer circuit. CONSTITUTION:A signal inverting an input is obtained by transistors (TRs) M11, 12 the signal is used to switch a TR Q11 and a signal in a same phase as the input switches TRs M13, Q12 to obtain the input buffer circuit of a conventional inverter form through the connection above. TRs M14, 15, 16 are not in use in this case. In obtaining the input buffer circuit of a Schmitt form, all TRs are used, the gate of the TR M11 is connected to the output to apply positive feedback and the TRs M14, 12, 16, 11 form the Schmitt trigger. In obtaining the buffer circuit of common mode, the TRs M11, 16 are not used in the Schmitt trigger circuit.

9. 发明专利

JPS61245624A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61245624A
公开(公告)日：1986-10-31
申请号：JP8637285
申请日：1985-04-24
申请人： HITACHI LTD
发明人： SHIBATA MANABU , URAGAMI KEN , KATONO SHINJI
IPC分类号： H03K19/173 , H03K5/00 , H03K5/13
摘要： PURPOSE:To form a delay element having a comparatively large delay time with a small number of circuit elements by using the resistance and the gate capacity of an MOS field effect transistor FET set previously into a basic cell to constitute a delay element. CONSTITUTION:A basic cell 1A contains an inverter INV1 using MOSFETs M1-M4; while a basic cell 1B contains an inverter INV2 using MOSFETs M1-M6. The gate capacities of MOSFETs M2-M6 within the cell 1A are connected in parallel with each other for production of a large capacity Ct. Then a CR type charging/discharging circuit is formed with the capacity Ct and resistances R1 and R2 in both cells 1A and 1B respectively. This charging/ discharging circuit is provided to a signal transmission path between both inverters INV1 and INV2 for formation of a delay element.

10. 发明专利

JPS6153826A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS6153826A
公开(公告)日：1986-03-17
申请号：JP17494884
申请日：1984-08-24
申请人： Hitachi Ltd
发明人： SUZUKI YASUNAGA , MATSUBARA TOSHIAKI , OWADA KAZUTO , KATONO SHINJI , NISHIO YOJI
IPC分类号： H03K19/003
CPC分类号： H03K19/00369
摘要： PURPOSE:To stabilize the logical threshold value of an internal circuit and eliminate the probability of malfunction by providing an IC circuit with the group line of a final output circuit and the ground line of an internal logical circuit, etc., independently of each other. CONSTITUTION:In the IC circuit, a ground bus G1 constitutes the common current circuit of an input buffer part 20 and an internal logical circuit 21 and is connected to the ground potential GND through a terminal T1. A ground bus G2 forms the current return circuit of only an output buffer part 22 and connected to the ground GND through a terminal T2, and the buses G1 and G2 are disconnected from each other. Even if a large sink current flows to the side of the output buffer part 22, or even if the current is switched at a high speed, the resulting transient effect extends only to the ground bus G2 and the ground bus G1 is not affected. Therefore, the potential of the bus G1 is held stable regardless of the state of the bus G2 and threshold values of the buffer part 20 and circuit part 21 are held stably, so that malfunction due to variation in threshold value is prevented.
摘要翻译：目的：为了稳定内部电路的逻辑门限值，通过为最终输出电路的组线和内部逻辑电路的接地线等提供IC电路，消除故障的概率。构成：在IC电路中，接地总线G1构成输入缓冲器部分20和内部逻辑电路21的公共电流电路，并通过端子T1连接到地电位GND。接地母线G2仅形成输出缓冲器部分22的电流返回电路，并通过端子T2连接到地GND，并且总线G1和G2彼此断开。即使大的电流电流流向输出缓冲器部分22的一侧，或者即使电流以高速切换，所产生的瞬态效应仅延伸到接地总线G2，并且接地总线G1不受影响。因此，无论总线G2的状态如何，总线G1的电位都保持稳定，并且缓冲部分20和电路部分21的阈值被稳定地保持，从而防止由于阈值变化引起的故障。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式