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21. 发明专利

JPS59107614A Voltage follower circuit 失效
标题翻译：电压下降电路
公开(公告)号：JPS59107614A
公开(公告)日：1984-06-21
申请号：JP21684982
申请日：1982-12-13
申请人： Hitachi Ltd
发明人： KOBAYASHI TOORU , HOSOSAKA HIROSHI , TANAKA TSUNEO
IPC分类号： H03F3/50 , H03F3/34
摘要： PURPOSE: To obtain a voltage follower circuit with high accuracy by controlling a current value of a curent source of a differential circuit so as to balance currents of a differential pair in response to the fluctuation of a power supply voltage.
CONSTITUTION: A current mirror current amplification factor M of transistors (TRs)Q
3 , Q
6 constituting a current mirror is taken as the unity. Let a battery voltage be V
s , an input voltage be V
i , an output voltage be VO, a power supply voltage be VG, and a fluctuation voltage be VBE, then a current flowing to resistors R
1 , R
2 is made equal in setting the resistance value R
s of the battery circuit to MR
1 /2, when the input voltage V
i is equal to the output voltage VO regardless of the value of the power supply voltage VG. Further, since the relation of V
s =V
i -VBE exists, a current flowing to the resistors R
1 , R
2 of TRs Q
1 , Q
2 is a half of a current I
s flowing to the resistor R
s . The relation of dV
i / dVBE≤1 exists actually, then the characteristic of the voltage follower circuit is dVO/dVBE≥1, allowing to compensate the fluctuating voltage VBE of the input voltage V
i by the power supply voltage VG.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过控制差分电路的电流源的电流值来获得高精度的电压跟随器电路，以便根据电源电压的波动平衡差动对的电流。构成：将构成电流镜的晶体管（TRs）Q3，Q6的电流镜电流放大系数M作为1。使电池电压为Vs，输入电压为Vi，输出电压为VO，电源电压为VG，波动电压为VBE，则将电阻R1，R2的电流设定为相等的电阻值当输入电压Vi等于输出电压VO时，电池电路的Rs为MR1 / 2，与电源电压VG的值无关。此外，由于存在Vs = Vi-VBE的关系，流入TRs Q1，Q2的电阻R1，R2的电流是流向电阻Rs的电流Is的一半。 dVi / dVBE <= 1的关系实际上存在，则电压跟随器电路的特性为dVO / dVBE> = 1，允许通过电源电压VG补偿输入电压Vi的波动电压VBE。

22. 发明专利

JPS5858751A INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5858751A
公开(公告)日：1983-04-07
申请号：JP15750981
申请日：1981-10-05
申请人： HITACHI LTD
发明人： TANAKA TSUNEO , KOIDE KAZUO , SATOU KAZUYOSHI , TAKAGI RIYUUICHI
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04 , H03K19/086
摘要： PURPOSE:To keep output voltage approximately constant regardless of voltage drops generated in the first wiring and the second wiring by setting the resistance ratio of the first wiring resistance and the second wiring resistance at value obtained by making the resistance ratio correspond to the resistance ratio of partial pressure resistance. CONSTITUTION:In a unit gate circuit, the operating currents of a current switch section flowing through resistors RCC, RE are kept at approximately constant value without regard to the switch operation of current changeover switch transistors TrQ41 or Q43 and Q5. On the other hand, operating currents flowing through an output circuit composed of a TrQC1 and a resistor R0 are made comparatively large value, and varied comparatively largely in response to the level of a signal Vout1 to be outputted. Accordingly, the output circuit generates comparatively large noises to power supply wiring in response to the change of the operating currents. When the power supply wiring layer of the output circuit is formed independently, there is no common impedance, and the application of undesirable noises to a current switch section and a reference voltage generating circuit in the unit gate circuit is prevented.

23. 发明专利

JPS61269529A LOGIC INTEGRATED CIRCUIT 失效
公开(公告)号：JPS61269529A
公开(公告)日：1986-11-28
申请号：JP11034085
申请日：1985-05-24
申请人： HITACHI LTD
发明人： TANAKA TSUNEO , KOBAYASHI TORU
IPC分类号： H03K19/018
摘要： PURPOSE:To attain high speed system operation by providing a circuit applying an externally supplied signal and a signal at the final stage of an internal logic and outputting the result and a circuit bypassing these circuits so as to use selectively either signal path. CONSTITUTION:A level conversion circuit applying level conversion to a signal supplied externally into a low amplitude signal and a bypass circuit 12 bypassing an external signal not through the circuit 11 are provided to the input section 1 of a logic integrated circuit to output the circuits 11, 12 to the internal logic section 2. The signal with a small amplitude signal from the logic section 2 is converted into a large amplitude level by a level conversion circuit 31 of the output section 3 and the result is outputted directly to the output terminal by the bypass circuit 32 not through the circuit 31. Then either signal path is selected and used by the input section 1 and the output section 3 so as to bring the system operation in high speed.

24. 发明专利

JPS61269528A OUTPUT CIRCUIT IN LOGIC LSI 失效
公开(公告)号：JPS61269528A
公开(公告)日：1986-11-28
申请号：JP11033985
申请日：1985-05-24
申请人： HITACHI LTD
发明人： TANAKA TSUNEO , KOBAYASHI TORU
IPC分类号： H03K19/0175 , H03K17/62 , H03K19/018 , H03K19/173
摘要： PURPOSE:To reduce the power consumption and to decrease the gate delay time in an output circuit by connecting >=2 output stages having different load drive capability to an output terminal selectively depending on the load. CONSTITUTION:A light load emitter follower EF1 and a heavy load emitter follower EF2 are provided corresponding to a current switch circuit CS of an emitter coupling logic ECL and a buffer gate Gb is connected to the pre-stage of the emitter follower EF2. further, an output terminal Pi is connected to output nodes n1, n2 of the emitter followers EF1, EF2 respectively. When the emitter follower EF1 is at light load, the output terminal Pi is selected and when at heavy load, a selective connecting part B is selected. In selecting the connection part B, the emitter follower EF2 selects the output terminal Pi via a buffer gate Gb. Then the power consumption of the ECL is decreased and the gate delay time in the output circuit is reduced.

25. 发明专利

JPS6016026A LOGIC LSI 失效
公开(公告)号：JPS6016026A
公开(公告)日：1985-01-26
申请号：JP12327483
申请日：1983-07-08
申请人： HITACHI COMPUTER ENG , HITACHI LTD
发明人： YOSHIDA SUKEHIRO , KOBAYASHI TOORU , TANAKA TSUNEO
IPC分类号： H03K19/173 , H03K19/013
摘要： PURPOSE:To improve the operating speed by the layout of elements so that each input transistor (TR) is located to adjacent parts of adjacent cells in a master slice LSI thereby decreasing the stray capacitance of wiring of the cells. CONSTITUTION:The basic cell structure of the ECL circuit of the master slice LSI is constituted by adjacent basic cells CL1, CL2, which are provided respectively with input transistors (TRs) Q11-Q13. Collectors and emitters of the TRs Q11-Q13 are connected in common and input signals Vin1-Vin5 are applied respectively to the TRs Q11-Q13. Further, a current switch circuit is constituted by the TRQ2 and the TRs Q11-Q13 between the emitters and collectors of common connection, and a reference voltage VBB is applied to the TRQ2. Further, a constant voltage is applied from the constant current source comprising a TRQ3 so as to constitute the emitter follower circuit with TRs Q4, 5. Then the stray capacitance between wirings in the basic cells CL1, CL2 is reduced thereby improving the operating speed of the LSI.

26. 发明专利

JPS59188233A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59188233A
公开(公告)日：1984-10-25
申请号：JP6216983
申请日：1983-04-11
申请人： Hitachi Ltd
发明人： KOTANI HIROSHI , TANAKA TSUNEO , KOBAYASHI TOORU , USAMI MITSUO , SATOU KAZUYOSHI , HOSOSAKA HIROSHI
IPC分类号： H03K19/086
CPC分类号： H03K19/086
摘要： PURPOSE:To realize low power consumption and high-speed operation by providing power source dependency matching with the power source dependency that an NTL (nonthreshold logical) circuit as an input buffer has as the reference voltage of an ECL circuit which receives a signal from the NTL circuit. CONSTITUTION:The ECL gate circuit which operates with a small signal amplitude and the NTC circuit which receives the input signal which normally has a small signal amplitude and is supplied externally are included, and the power source dependency matching with the source voltage dependency of the signal of the NTL circuit is provided as the reference voltage of the ECL gate circuit. The NTL circuit includes a transistor (TR) Q1 as an input TR in differential relation with a TRQ2, and a feedback signal is applied to the base of the other TRQ2. Then, feedback resistances R4 and R5 generating a feedback signal to be supplied to a load and the base of the TRQ2 are provided to the emitter of the output TRQ3. Then, the TRQ3 sends out an input signal to the ECL gate circuit.
摘要翻译：目的：通过提供与作为输入缓冲器的NTL（非阈值逻辑）电路作为ECL电路的参考电压的电源依赖性依赖性来实现低功耗和高速操作，其接收来自 NTL电路。构成：包含以小信号幅度工作的ECL门电路和接收通常具有小信号幅度并从外部提供的输入信号的NTC电路，并且电源依赖性与信号的源电压依赖性相匹配的NTL电路作为ECL门电路的参考电压。 NTL电路包括作为与TRQ2差分关系的输入TR的晶体管（TR）Q1，并且反馈信号施加到另一个TRQ2的基极。然后，向输出TRQ3的发射极提供反馈电阻R4和R5，其产生要提供给负载的反馈信号和TRQ2的基极。然后，TRQ3向ECL门电路发出一个输入信号。

27. 发明专利

JPS59105348A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS59105348A
公开(公告)日：1984-06-18
申请号：JP21390682
申请日：1982-12-08
申请人： Hitachi Ltd
发明人： TANAKA TSUNEO , KOBAYASHI TOORU , HATSUTA YASUSHI , HOSOE HIDEYUKI
IPC分类号： H01L21/31 , H01L21/60 , H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05124 , H01L2224/05624 , H01L2924/01013
摘要： PURPOSE:To enable to sufficiently secure the effective area by preventing the disconnection of an Al layer for wiring by a method wherein one side of the electrode pad on the side wherein the Al layer for wiring is extended is positioned inward from at least a recess of the final protection film. CONSTITUTION:The Al layer 12 for wiring to mutually connect each circuit element is formed on the surface of a semiconductor substrate 11, and an interlayer insulation layer 15 is formed thereon, resulting in the protection of the Al layer 12. Next, the interlayer insulation layer 15 is removed at the position of an electrode pad, the second Al layer 13 for a pad is formed from above it to the part corresponding to the electrode pad, and further the final protection film 14 is formed thereon. At this time, the recess 14a is formed along the inside edge of the second Al layer 13. Then, a photo resist layer 17 is formed on the final protection film 14. In this case, the periphery of an aperture 18 is positioned some inside from the outer edge of the second Al layer 13. Particularly as far as the side 18a on the side wherein the Al layer 12 is extended is concerned, it is stretched inward and then positioned inward from the recess 14a of the final protection film 14.
摘要翻译：目的：为了能够通过防止用于布线的Al层的断开来充分确保有效面积，其中，其中用于布线的Al层的一侧的电极焊盘的一侧位于从布线的延伸的至少一个凹部最后的保护膜。构成：在半导体基板11的表面上形成有用于相互连接各电路元件的布线用的Al层12，在其上形成层间绝缘层15，从而保护Al层12.接下来，层间绝缘在电极焊盘的位置处去除层15，用于焊盘的第二Al层13从其上方形成到与电极焊盘对应的部分，并且在其上形成最终保护膜14。此时，凹部14a沿着第二Al层13的内边缘形成。然后，在最终保护膜14上形成光致抗蚀剂层17.在这种情况下，孔18的周边位于一些内部特别地，就其中Al层12延伸的一侧的侧面18a而言，它被向内拉伸，然后从最终保护膜14的凹部14a向内定位。

28. 发明专利

JPH0151066B2 失效
公开(公告)号：JPH0151066B2
公开(公告)日：1989-11-01
申请号：JP2439682
申请日：1982-02-19
申请人： HITACHI LTD
发明人： TANAKA TSUNEO , KOBAYASHI TOORU , KOIDE KAZUO , HOSOSAKA HIROSHI
IPC分类号： H01L21/822 , G05F3/30 , G11C11/401 , G11C11/407 , H01L21/3205 , H01L21/82 , H01L21/8222 , H01L23/52 , H01L27/04 , H01L27/06 , H01L27/082 , H01L27/118

29. 发明专利

JPS61269524A LOGIC CIRCUIT 失效
公开(公告)号：JPS61269524A
公开(公告)日：1986-11-28
申请号：JP11034385
申请日：1985-05-24
申请人： HITACHI LTD
发明人： TANAKA TSUNEO , KOBAYASHI TORU
IPC分类号： H03K17/60 , H03K19/013 , H03K19/018
摘要： PURPOSE:To improve the operating time of the entire circuit by providing a bias means using an output from a logic section so as to make the output of an output transistor (TR) conductive tentatively thereby decreasing the gate delay time of the output circuit of a logic LSI. CONSTITUTION:The 2nd TR Q7 is connected between an emitter of the 1st output TR Q6 connected to an output node n0 of a differential logic section DL of a logic LSI and a power supply VEE and the TRs Q6, Q7 constitute an output stage. Further, a bias circuit composing of resistors R1-R3 supplying a base current only at the trailing of the output to the TR Q7 is provided between the output node n0 and the power supply VEE. Then an impedance conversion TR Q8 and a potential difference detection TR Q9 detecting the potential difference between nodes n1 and n2 are provided in parallel with the resistors R1 and R2. Then the output of the logic section DL conducts tentatively the output of the output TR Q7 so as to decrease the gate delay time of the output circuit thereby speeding up the operating time of the entire LSI.

30. 发明专利

JPS60223325A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60223325A
公开(公告)日：1985-11-07
申请号：JP7846384
申请日：1984-04-20
申请人： HITACHI LTD
发明人： KOTANI HIROSHI , TANAKA TSUNEO , SHIRATORI FUMIHIKO
IPC分类号： H03K19/086
摘要： PURPOSE:To attain substantial low power consumption and high speed operation by providing dividing points being nearly the same voltage when an input signal is at a low level so as to divide respectively a common emitter of a differential transistor (TR) and a resistor means provided to an emitter of an emitter follower output TR and connect both the dividing points with a resistor means. CONSTITUTION:When the input signal fed to an input terminal IN is at a low level, the potential of the dividing point A of emitter resistors RE1, RE2 and the dividing point B of load resistors RL1, RL2, is nearly the same and no current flows to a resistor R4 connecting both the dividing points A and B. When the input signal is at a high level, a current i2 flows from the dividing point B to the dividing point A, a current 1i flowing to a collector of the differential TRQ1 is decreased by the share and a current i3 flowing to an output TRQ3 is increased. Then an ineffective current flowing to the collector of the Q1 is reduced and the operating current flowing to the Q3 is increased, thereby increasing the drive capability and realizing high speed operation.

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