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1. 发明专利

JPS6413482A LOGIC LSI 失效
公开(公告)号：JPS6413482A
公开(公告)日：1989-01-18
申请号：JP16866587
申请日：1987-07-08
申请人： HITACHI LTD
发明人： KAWASHIMA MASATOSHI , TAKECHI MAKOTO , KOTANI HIROSHI
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K3/037 , H03K19/173
摘要： PURPOSE:To easily diagnose logic LSIs by connecting master-slave system FF circuits in series with the data input side and output side of a circuit formed of the logic LSIs in combination. CONSTITUTION:Test data SF for testing a combinational circuit 7 is set in FF circuits 1 and 2 first. Then test mode clock signals SCK1 and SCK2 are held at a high level alternately and the test data SD of the circuits 7 and 8 are set in FFs 1, 2, 3 and 3 in order. This test pattern is supplied to the circuits 7 and 8 through a slave latch circuit. Then when an operation control signal SCAN is held at a low level, switches SW1-SW6 input normal mode data D to the respective FFs and the signals SCK1 and SCK2 are held at the low level. Those signals SCK1 and SCK2 are held at the high level alternately to read out the data fetched in the FFs 3, 4, 5 and 6.

2. 发明专利

JPS6329276A LOGIC LSI 失效
公开(公告)号：JPS6329276A
公开(公告)日：1988-02-06
申请号：JP17162586
申请日：1986-07-23
申请人： HITACHI LTD
发明人： KAWASHIMA MASATOSHI , TAKECHI MAKOTO , KOTANI HIROSHI
IPC分类号： G01R31/28 , G01R31/3185
摘要： PURPOSE:To easily diagnose an LSI by dividing the logic LSI into plural combinational circuits, connecting a master-slave type circuit which has series- connected FF circuits to respective data input/output sides, and providing an operation control pin for test mode setting to a master latch circuit which constitutes the FF circuits. CONSTITUTION:The logic LSI is diagnosed effectively by being divided into small-scale combination circuits, so combinational circuits 7 and 8 divided into blocks are provided. Then, FF circuits 1 and 2, and 3 and 4 which are connected in series are provided on the input/output side of the circuit 7, and the circuits 3 and 4 are used in common as FF circuits on the input side of the circuit 8 while FF circuits 5 and 6 which are connected in series are provided on the output side. Here, the circuits 1-6 each consists of a master latch circuit 11 and a slave latch circuit 12 and an input pin D and a clock pin CK are made effective in normal mode. Further, an input pin SD and a clock pin SCK 1 are made effective in test mode to facilitate the LSI diagnosis.

3. 发明专利

JPS59224923A CONSTANT VOLTAGE GENERATING CIRCUIT 失效
公开(公告)号：JPS59224923A
公开(公告)日：1984-12-17
申请号：JP9782583
申请日：1983-06-03
申请人： HITACHI LTD
发明人： KOBAYASHI TOORU , KOTANI HIROSHI
IPC分类号： H03K19/00 , G05F3/30 , H03K19/086
摘要： PURPOSE:To improve the power supply voltage characteristic by providing a transistor (TR) absorbing a current corresponding to a power supply voltage fluctuation among currents flowing to a prescribed npn TR in a constant voltage generating circuit. CONSTITUTION:A constant current is formed by providing a resistor R6 receiving a constant voltage produced as a base-emitter voltage difference of a couple of TRs Q1, Q2 of the current mirror form caused by different emitter current density to an emitter of a TRQ2 at the output side. A constant voltage is obtained from other terminal of a resistor R7 provided to a collector of the TRQ2 by flowing the said constant current to the resistor R7. A TRQ4 for absorbing current is provided to allow a current flowing to a TRQ3 to be immune to the fluctuation of a power supply voltage -Vee in the constant voltage generating circuit as above. Thus, the improvement of the power supply voltage characteristic is attained.

4. 发明专利

JPS63181526A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63181526A
公开(公告)日：1988-07-26
申请号：JP1232087
申请日：1987-01-23
申请人： HITACHI LTD
发明人： KOTANI HIROSHI
IPC分类号： H03K19/0185 , H03K17/00 , H03K19/00 , H03K19/173
摘要： PURPOSE:To prevent the occurrence of a DC current and the occurrence of an intermediate potential between logic circuits by making a first switch MOSFET and a second MOSFET in ON states with an output signal from an exclusive 'or' circuit. CONSTITUTION:The first switch MOSFETQ1 and the second switch MOSFETQ2 are provided; the former switch respectively combines the output terminals of two logic circuits G1 and G2 whose actions are controlled according to an output control signal, to a common output node and the latter one supplies low level to the common output node. By providing the exclusive OR circuit EXN which detects a simultaneous output state and a simultaneous non-action state in receiving the output control signal, the first switch MOSFETQ1 and the second MOSFETQ2 are made to be in ON states according to the output signal. Even if the concurrence between action state and non-action state occurs between the logic circuits G1 and G2, the occurrence of the DC current between the logic circuits G1 and G2 can be prevented by means of the OFF state of the first switching element Q1 and the occurrence of the intermediate potential can be prevented by means of the ON state of the second switching element Q2.

5. 发明专利

JPS6012751A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6012751A
公开(公告)日：1985-01-23
申请号：JP11829183
申请日：1983-07-01
申请人： HITACHI LTD
发明人： KOTANI HIROSHI , KOBAYASHI TOORU , USAMI MITSUO , HOSOSAKA HIROSHI
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8222 , H01L27/04 , H01L27/082 , H01L27/118 , H01L27/06
摘要： PURPOSE:To obtain multi-functions with the minimum number of elements by a method wherein an input circuit and an output circuit are prepared for every given input-output terminal, and then input circuits are arranged and connected to terminals, respectively, in the construction of a desired circuit by the connection of either one circuit to the input-output terminal. CONSTITUTION:A logic circuit having desired logic functions is constructed in an Si substrate 1 by a master slicing method, and a plurality of bonding pads P1-P6 are formed by corresponding to those, each of which is then connected to an input-output pin. In this construction, a basic input circuit cell CCi and a basic output circuit cell CCo are put into a pair and connected to the pad P1; thereafter one-pairs of the same construction are connected to respective pads of the pad P2 and the rest. Here, a plurality of transistor elements, resistance elements, and the like are formed in the CCi and the CCo in such a manner that a desired input circuit or output circuit can be constituted, respectively, and accordingly the wiring connection between adjacent input circuits is facilitated.

6. 发明专利

JPH08180095A DELAY FAULT SIMULATION METHOD AND DELAY FAULT ANALYZING DEVICE 失效
公开(公告)号：JPH08180095A
公开(公告)日：1996-07-12
申请号：JP33484594
申请日：1994-12-20
申请人： HITACHI LTD
发明人： GOTO MASAKI , KOTANI HIROSHI
IPC分类号： G06F11/25 , G06F17/00 , G06F17/50 , G06F19/00 , G06Q50/00 , G06Q50/04
摘要： PURPOSE: To provide a delay fault simulation method with which a delay fault can be simulated for a degenerate fault model. CONSTITUTION: Delay cells 31 and 32 are inserted into the signal path of a circuit to be simulated through a computer. One cell assumes a delay fault on a rising edge and the other cell assumes a delay fault on a falling edge. Concerning the respective delay cells, either a delay state to transmit a signal with a delay amount for assuming the delay fault or a normal state to transmit a signal without generating any delay fault can be selected corresponding to the logical values of selecting terminals N7 and N8. A degenerate fault simulation is performed while assuming the selecting terminal of the delay cell in the delay state as a degenerate fault node, a fault caused by the degenerate fault node assumed in this simulated result is replaced with the delay fault at the signal path, and a fault position to be made correspondent to the real test result is analyzed.

7. 发明专利

JPS62174668A FLIP-FLOP CIRCUIT 失效
公开(公告)号：JPS62174668A
公开(公告)日：1987-07-31
申请号：JP1566486
申请日：1986-01-29
申请人： HITACHI LTD
发明人： SHIRATORI FUMIHIKO , KOTANI HIROSHI
IPC分类号： H03K3/037 , G01R31/28
摘要： PURPOSE:To reduce delay caused by the load of an FF circuit by connecting a gate circuit which controls the output of a master latch circuit and a slave latch circuit which is used only during a test to different output terminals of the master latch circuit respectively. CONSTITUTION:One input terminal of a gate 1 is connected to the output terminal Q of the master latch circuit LAT1 and the data input terminal D of the slave latch circuit LAT2 is connected to the output terminal Q. Further, one input terminal of a gate 3 is connected to the output terminal Q of the circuit LAT2 and a control signal and its inverted signal are inputted to other-terminal sides of the gates 1 and 3 respectively to control the output state of data. Thus, the gate 1 and circuit LAT2 are connected dispersedly to the terminals Q and Q of the circuit LAT1, so the side of the terminal Q of the circuit LAT1 drives only the gate 1 in normal operation. Consequently, the load on the output terminal Q is reduced and the delay due to the load is reduced.

8. 发明专利

JPS60223325A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60223325A
公开(公告)日：1985-11-07
申请号：JP7846384
申请日：1984-04-20
申请人： HITACHI LTD
发明人： KOTANI HIROSHI , TANAKA TSUNEO , SHIRATORI FUMIHIKO
IPC分类号： H03K19/086
摘要： PURPOSE:To attain substantial low power consumption and high speed operation by providing dividing points being nearly the same voltage when an input signal is at a low level so as to divide respectively a common emitter of a differential transistor (TR) and a resistor means provided to an emitter of an emitter follower output TR and connect both the dividing points with a resistor means. CONSTITUTION:When the input signal fed to an input terminal IN is at a low level, the potential of the dividing point A of emitter resistors RE1, RE2 and the dividing point B of load resistors RL1, RL2, is nearly the same and no current flows to a resistor R4 connecting both the dividing points A and B. When the input signal is at a high level, a current i2 flows from the dividing point B to the dividing point A, a current 1i flowing to a collector of the differential TRQ1 is decreased by the share and a current i3 flowing to an output TRQ3 is increased. Then an ineffective current flowing to the collector of the Q1 is reduced and the operating current flowing to the Q3 is increased, thereby increasing the drive capability and realizing high speed operation.

9. 发明专利

JPS6020637A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6020637A
公开(公告)日：1985-02-01
申请号：JP12765883
申请日：1983-07-15
申请人： HITACHI LTD
发明人： KOBAYASHI TOORU , KOTANI HIROSHI , USAMI MITSUO , HOSOSAKA HIROSHI
IPC分类号： H03K19/086 , H03K19/20
摘要： PURPOSE:To prevent migration and to expand signal level margin by connecting a pair of load resistors to both terminals where a wiring resistor of an optional output terminal of wiring constituting a wired logic is maximized to disperse the concentration of a current flowing to the wiring. CONSTITUTION:The wired logic is constituted by connecting selectively an emitter of an inverting output transistor (TR) Q6 or a non-inverting side output TR Q5 of ECL gate circuits G1-Gn comprising TRs Q1-Q6 by means of wiring L. In forming a wired logical gate Gw by the wiring L, two load resistors RL prepared respectively for the emitter of the inverting output TR of the gate G1 and the gate Gn being both the longest ends of the said wiring are connected respectively as series constitution. Thus, the load resistor is connected respectively at two points where the wiring resistance between two points are maximized.

10. 发明专利

JPS59231918A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS59231918A
公开(公告)日：1984-12-26
申请号：JP10583583
申请日：1983-06-15
申请人： HITACHI LTD
发明人： KOTANI HIROSHI , KOBAYASHI TOORU , USAMI MITSUO
IPC分类号： H03K19/086
摘要： PURPOSE:To improve the SN of the IC by forming a resistive element in an input stage onto an island of N layer on which transistor (TR) elements of the input stage are formed so as to prevent the effect of fluctuation of a power supply voltage at an output stage from being given to the input stage through the resistive element. CONSTITUTION:When a TR formed on the island of N layer is a TRQ1 or Q2 in a current switch CS, a P diffusion layer formed on this island corresponds to a resistor R1 or R2. On the other hand, when the TR formed on this island is a TRQ4 or Q5 for emitter follower, the diffusion layer 8 on this island corresponds to a resistor R4 or R5 for emitter follower. Further, the resistors R1- R3 constituting this current switch circuit are formed on the island of N layer on which the TRQ1-Q3 constituting this circuit are formed. Thus, even if a power supply voltage vcc1 is fluctuated because of a large current flowing to the TRsQ4, Q5, the configuration precludes the possibility of noise from giving to the current switch circuit side.

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