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2. 发明专利

JPS61500400A JPS61500400A - 失效
公开(公告)号：JPS61500400A
公开(公告)日：1986-03-06
申请号：JP50396784
申请日：1984-10-22
IPC分类号： H03K19/013 , H03K19/086
CPC分类号： H03K19/0136 , H03K19/086 , H03K19/0866

3. 发明专利

JPS5913425A Logical circuit with test circuit 失效
标题翻译：具有测试电路的逻辑电路
公开(公告)号：JPS5913425A
公开(公告)日：1984-01-24
申请号：JP12267482
申请日：1982-07-14
申请人： Fujitsu Ltd
发明人： FUNADOGAWA HITOSHI , ODA MASAHIRO
IPC分类号： H03K19/086
CPC分类号： H03K19/086
摘要： PURPOSE:To test a highly integrated circuit precisely by providing an emitter coupling type logical circuit (ECL) with a test circuit to control the ECL by a logical signal level from the external independently of an input signal to the ECL and set up the output of the ECL to the level corresponding to zero of the logical signal. CONSTITUTION:A transistor (TR) T6 is connected to the base circuit of a TR T4 of an OR output circuit and a TR T7 is connected to the base circuit of a TR T5 of a NOR output circuit. When a signal ''1'' is applied to a test terminal, the TRs T6, T7 are connected and the base potential of the TRs T4, T5 is shifted to the negative side, so that the base potential of the TRs T4, T5 are reduced and both the OR and NOR output terminals are turned to ''0''. Since said operation is not restricted by the operation of the Trs T1, T2, T3, the operation has no relation to the input conditions and there is no electrical bad influences to the original circuit.
摘要翻译：目的：为了通过提供具有测试电路的发射极耦合型逻辑电路（ECL）来精确测试高度集成的电路，通过独立于ECL的输入信号从外部的逻辑信号电平来控制ECL，并设置输出 ECL到对应于逻辑信号零的电平。构成：晶体管（TR）T6连接到OR输出电路的TR T4的基极，TR T7连接到NOR输出电路的TR T5的基极。当信号“1”被施加到测试端子时，TRs T6，T7被连接，并且TR T4，T5的基极电位偏移到负侧，使得TRs T4，T5的基极电位并且OR和NOR输出端子都变为“0”。由于所述操作不受Trs T1，T2，T3的操作的限制，操作与输入条件无关，并且对原始电路没有电不良影响。

4. 发明专利

JPS58215826A Semiconductor logical circuit 失效
标题翻译：半导体逻辑电路
公开(公告)号：JPS58215826A
公开(公告)日：1983-12-15
申请号：JP9971882
申请日：1982-06-10
申请人： Nec Corp
发明人： NOKUBO JIYOUJI
IPC分类号： H03K19/086
CPC分类号： H03K19/086
摘要： PURPOSE:To make the switching of a logical level easy, by providing a program element programmed with a voltage or a current applied to a collector terminal for changing the logic of an output with the information of the program element. CONSTITUTION:An ECL logical circuit is provided with a terminal having a maximum potential and a collector terminal of an output transistor (TR) Q10, signals P1-P3 to be controlled are controlled with inverter TRs Qp4-Qp6, and when the TRs Qp4-Qp6 are turned on, the circuit is taken as the 10k-series and when off, it is taken as the 100k-series. This logical circuit is provided with a circuit P storing the switching information of the 10k and the 100k, having the programmable element RF. Further, a voltage applied to the element RF is changed for the 10k-series and the 100k-series, the output logic is changed depending on the information of the element RF, allowing to switch the logial level easily.
摘要翻译：目的：为了使逻辑电平的切换变得容易，通过提供编程有电压或电流的程序单元，用于通过程序单元的信息来改变输出的逻辑。构成：ECL逻辑电路设置有具有输出晶体管（TR）Q10的最大电位和集电极端子的端子，要被控制的信号P1-P3由反相器TRs-Qp4-Qp6控制，并且当TRs Qp4- Qp6开启，电路为10k系列，关闭时为100k系列。该逻辑电路设置有存储具有可编程元件RF的10k和100k的开关信息的电路P. 此外，对于10k系列和100k系列，施加到元件RF的电压改变，输出逻辑根据元件RF的信息而改变，允许容易地切换逻辑电平。

5. 发明专利

JPS58202626A Logical circuit 失效
标题翻译：逻辑电路
公开(公告)号：JPS58202626A
公开(公告)日：1983-11-25
申请号：JP8597982
申请日：1982-05-21
申请人： Nec Corp
发明人： HIRANO YOUJI
IPC分类号： H03K19/08 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K19/013
摘要： PURPOSE:To secure good switching characteristics with no saturation of an input transistor despite application of an input signal of large amplitude, by providing a reverse conducting transistor having a voltage clamping capacity to the input signal voltage. CONSTITUTION:This logical circuit extracts an NOT logical output out of the collector of an input transistor TRQ1 and at the same time the acknowledge logical output of a reference TRQR. In this circuit, the change DELTAVC of the collector potential of a driving current control TRQS is controlled to the value approximately equal to the emitter-base forward voltage VP of a reverse conducting transistor TRQP even though the input signal level has a big change from a low level to a high level since the TRQP contains the voltage clamping capacity. Thus it is possible to maintain a high-speed logical operation with no saturation of the TRQI even to a large input amplitude signal.
摘要翻译：目的：通过提供具有对输入信号电压的钳位电容的反向导通晶体管，以确保良好的开关特性，尽管施加了大振幅的输入信号，输入晶体管没有饱和。构成：该逻辑电路从输入晶体管TRQ1的集电极中提取出NOT逻辑输出，同时提取参考TRQR的确认逻辑输出。在该电路中，驱动电流控制TRQS的集电极电位的变化DELTAVC被控制为大致等于反向导通晶体管TRQP的发射极 - 基极正向电压VP的值，即使输入信号电平与低电平到高电平，因为TRQP包含电压钳位能力。因此，即使对于大的输入幅度信号，也可以保持没有TRQI的饱和的高速逻辑运算。

6. 发明专利

JPS5769932A Current switching type logical circuit 失效
标题翻译：电流开关型逻辑电路
公开(公告)号：JPS5769932A
公开(公告)日：1982-04-30
申请号：JP14713180
申请日：1980-10-21
申请人： Nec Corp
发明人： TASAI SADAJI
IPC分类号： H03K19/086
CPC分类号： H03K19/086
摘要： PURPOSE:To eliminate the need for a power supply circuit and to achieve low power consumption, by using the connecting point of two resistors connected in series between a positive output terminal and a negative output terminal of a logical circuit. CONSTITUTION:A constant current source IE is connected to an emitter common connecting terminal 7 between an input side transistor (TR)Q1 and a reference voltage side TRQ2. Collector resistors R1, R2 are respectively connected to the collector of the TRsQ1, Q2. A terminal 4 is taken as a positive output terminal and a terminal 3 is as a negative output terminal, where each signal can be picked up. A reference voltage applied to the base of the reference voltage TRQ2 can be picked up from the connecting point 6 between resistors R3 and R4 connected in series between the positive and negative output terminals 4 and 3.
摘要翻译：目的：通过使用逻辑电路的正输出端子和负输出端子串联连接的两个电阻器的连接点，消除对电源电路的需要并实现低功耗。构成：恒流源IE连接到输入侧晶体管（TR）Q1和参考电压侧TRQ2之间的发射极公共连接端子7。集电极电阻R1，R2分别连接到TRsQ1，Q2的集电极。将端子4作为正输出端子，端子3作为负输出端子，其中可以拾取每个信号。施加到参考电压TRQ2的基极的参考电压可以从连接在正和负输出端子4和3之间的电阻器R3和R4之间的连接点6拾取。

7. 发明专利

JPS5761335A Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：JPS5761335A
公开(公告)日：1982-04-13
申请号：JP13627580
申请日：1980-09-30
申请人： Nec Corp
发明人： OKADA KENJI
IPC分类号： H03K19/086 , H03K19/20
CPC分类号： H03K19/086
摘要： PURPOSE:To stabilize the operation by giving relief to the level difference and by expanding noise margin, by disposing resistors for emitter flower on the both function blocks which form the wired.OR logic. CONSTITUTION:A resistor RE for an emitter flower is connected to both transistors TA and TB for output of logical function blocks A and B as REA and REB. Therefore, the worst condition of output level fluctuation of wired.OR logic is a half of the conventional extent of fluctuation. Even if transistors which constitute the wired.OR are increased, the extent of fluctuation is the same. In this way, stable ECL gate type master slice system LSI with small extent of fluctuation and having a good yield can be obtained.
摘要翻译：目的：通过在形成有线或逻辑的两个功能块上设置发射器花的电阻，通过减轻电平差异和扩大噪声容限来稳定操作。构成：用于发射体花的电阻器RE连接到晶体管TA和TB，用于输出逻辑功能块A和B作为REA和REB。因此，有线或逻辑逻辑的输出电平波动的最差条件是常规波动幅度的一半。即使构成有线元件的晶体管增加，波动幅度也相同。以这种方式，可以获得具有较小波动并且具有良好产量的稳定的ECL门型主片系统LSI。

8. 发明专利

JP3735406B2 Logic circuit 失效
公开(公告)号：JP3735406B2
公开(公告)日：2006-01-18
申请号：JP8658496
申请日：1996-04-09
申请人：コーニンクレッカフィリップスエレクトロニクスエヌヴィKoninklijke Philips Electronics N.V.
发明人：デュフールイブ
IPC分类号： H03K19/086 , G05F3/16 , H03K19/00 , H03K19/003
CPC分类号： H03K19/086 , G05F3/16 , H03K19/001 , H03K19/00376

9. 发明专利

JPS61127226A Emitter coupled logic circuit 失效
标题翻译：发射机耦合逻辑电路
公开(公告)号：JPS61127226A
公开(公告)日：1986-06-14
申请号：JP25966485
申请日：1985-11-18
申请人： Advanced Micro Devices Inc
发明人： NITSUKUHIRU SHII MEIZAMUDAA , DEIBUITSUDO EICHI BII II
IPC分类号： H03K17/60 , H03K19/003 , H03K19/086
CPC分类号： H03K19/086 , H03K17/603 , H03K19/00353 , H03K19/0866

10. 发明专利

JPS6156511A Potting circuit 失效
标题翻译：电路电路
公开(公告)号：JPS6156511A
公开(公告)日：1986-03-22
申请号：JP6493885
申请日：1985-03-28
申请人： Torirojii Computer Dev Paatona
发明人： ROBAATO MAIKURU RAINSHIYUMITSU
IPC分类号： H03K19/00 , H03K19/086 , H03K19/177 , H03K19/23
CPC分类号： H03K19/23 , H03K19/086 , H03K19/0866

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