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11. 发明专利

JPH08147341A LAYOUT DESIGNING DEVICE FOR STANDARD CELL AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08147341A
公开(公告)日：1996-06-07
申请号：JP28195794
申请日：1994-11-16
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO , YANO JUNICHI , YAMAGUCHI SEIJI
IPC分类号： H01L21/82 , G06F17/50
摘要： PURPOSE: To provide a standard cell and a semiconductor integrated circuit capable of wiring the metallic wiring of a power source and the metallic wiring of the ground in the layout designing device for the standard cell and the semiconductor integrated circuit and in addition, automatically optimizing the widths of the metallic wirings of the power source and the ground corresponding to the current quantity to be spend by the standard cell. CONSTITUTION: The layout designing device for the semiconductor integrated circuit is provided with a standard cell arranging means 200a for arranging plural standard cells, a first wiring means 200b wiring so as to connect the electrical connection of the power source and the ground within the standard cell, and a second wiring means 200c wiring so as to connect the electrical connection of the power source and the ground between the standard cells.

12. 发明专利

JPH07226670A CMOS LEVEL SHIFT CIRCUIT 失效
公开(公告)号：JPH07226670A
公开(公告)日：1995-08-22
申请号：JP1714694
申请日：1994-02-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： GION MASAHIRO , NINOMIYA KAZUKI , MIYAKE JIRO , TOYOKURA MAKI , UCHIUMI NORIO
IPC分类号： H03K5/02 , H03K17/16 , H03K19/0185
摘要： PURPOSE:To perform the low power consumption of a circuit by preventing through current from flowing in a CMOS level shift circuit. CONSTITUTION:First and second N type MOS transistors 14 and 15 are serially connected between power source voltage and ground. The signal inputted from an external input terminal 11 is transmitted to the gate of a second N type MOS transistor 15 via a first inverter 12 and is transmitted to the gate of the first N type MOS transistor 14 via the first and second inverters 12 and 13. Each drain of the first and second N type MOS transistors 14 and 15 is connected with the a high output positive feedback circuit composed of a third inverter and a P type MOS transistor.

13. 发明专利

JPH0495168A LAYOUT VERIFYING METHOD AND IT'S DEVICE 失效
公开(公告)号：JPH0495168A
公开(公告)日：1992-03-27
申请号：JP21090490
申请日：1990-08-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO
IPC分类号： G06F17/50
摘要： PURPOSE:To efficiently detect the node in which noncoincidence of connection occurs by extracting all attributes for showing the node name in which the total of the number of circuit element connected to each node exceeds a prescribed threshold. CONSTITUTION:this device is provided with a net list connecting information extracting means 1, a layout connecting information extracting means 2, an attribute extracting means 3, an adding means 4, and a collating means 5. In such a state, attributes for showing the node name in which the total of the number of transistors and the number of gates connected to each node of a circuit element of a net list of a semiconductor integrated circuit exceeds a certain threshold are all extracted, added newly to the corresponding node of connecting information of the circuit element of a layout, and a connecting collation of connecting information of the circuit element extracted from the net list, and connecting information of the circuit element extracted from the processed layout is executed by using the attribute for showing a fact that it is the initial corresponding node and the attribute for showing the extracted node name. In such a way, the node in which noncoincidence of connection occurs can efficiently be detected.

14. 发明专利

JPH02256005A OPTICAL WIRING DEVICE 失效
公开(公告)号：JPH02256005A
公开(公告)日：1990-10-16
申请号：JP7881689
申请日：1989-03-29
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YONEZAWA HIROKAZU , ISHII HIDEO , UCHIUMI NORIO , NAGAOKA TAKAHIRO , URANO YOSHINORI , KANO SHINGO , TANAKA TETSUYA
IPC分类号： G02B6/122 , G02B6/12
摘要： PURPOSE:To execute an optical wiring at the size to allow mounting on a package by forming the device in such a manner that the light emitted from a light source at the time of operation is made incident to a dielectric thin film, is bent to a semiconductor element side in the thin film, is once received and reflected by the optical function element on the semiconductor element, is again guided in the thin film and is received by a photodetector. CONSTITUTION:The light emitted from the light source 4 is made incident nearly horizontally to the low-refractive index region of the dielectric thin film 1 and is bent to the semiconductor element 2 side of a high refractive index by the effect of a distributed refractive index as the light is guided in the thin film 1. As a result, the light finally arrives at the optical function element 6 and is received by this element. The light is modulated and reflected inaccordance with the signal of the semiconductor element 2. The light is guided again through the thin film 1 in the route symmetrical with the route starting from the light source 4 to the optical function element 6 and is emitted nearly horizontally from the low refractive index region until finally the light is received in a photodetector 5. Since the dielectric thin film is used for the medium to guide the light, the device is disposed nearly flatly and the optical wiring is executed at the side to allow the mounting to the package.

15. 发明专利

JP2000148595A MEMORY DEVICE WITH DATA PROTECTION FUNCTION 失效
公开(公告)号：JP2000148595A
公开(公告)日：2000-05-30
申请号：JP31382698
申请日：1998-11-05
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HORI YASUNORI , UCHIUMI NORIO
IPC分类号： G06F12/14 , G06F9/06 , G06F21/22 , G06F21/24
摘要： PROBLEM TO BE SOLVED: To realize the secrecy of data, energy saving, space saving, and cost reduction. SOLUTION: The memory device is provided with a storage circuit 6 for temporarily storing ROM data outputted from a memory cell 5 in accordance with an output enable signal 4, a dummy data part 7 for storing optional dummy data, a logical circuit 8 for output-ting a select signal 9 at the time of detecting the first leading edge of the output enable signal 4, and a selector circuit 10 for selecting either one of the ROM data temporarily stored in the circuit 6 and the dummy data stored in the dummy data part 7 and outputting the selected data. The selector circuit 10 is constituted so as to output the dummy data stored in the dummy data part 7 when the select signal 9 is in an 'H' level. Since the storing address of the ROM data outputted to the external is deviated, the secrecy of the ROM data can be realized.

16. 发明专利

JPH08161891A STANDARD CELL AND LAYOUT DESIGN DEVICE 失效
公开(公告)号：JPH08161891A
公开(公告)日：1996-06-21
申请号：JP30361694
申请日：1994-12-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YANO JUNICHI , UCHIUMI NORIO , YAMAGUCHI SEIJI
IPC分类号： G11C11/41 , G06F17/50 , H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PURPOSE: To obtain a layout design in which a layout block area is small by applying electric connection information of a standard cell on intersection of lattice information and making wirings including components of the horizontal direction in the standard cell easy. CONSTITUTION: A feed-through wiring 118 enters from the upper part on the lattice 102 of a standard cell 101 and passes on the grid 104 of the cell via the intersected point between the lattice 102 and a grid 107 and the intersected point between a lattice 104 and the lattice 107 toward an other standard cell 101. When the standard cell 101 is designed, in the case a wiring passed a certain lattice, a wiring, the size of an input-output pin and the thickness of the wiring laid on the adjacent grid are speculated. Thus, at the time of drawing the wiring 118, the wiring is drawn by wiring it on lattices on which the wiring and the input-output pin are not laid in the cell 101.

17. 发明专利

JPH06342376A INFORMATION PROCESSOR 失效
公开(公告)号：JPH06342376A
公开(公告)日：1994-12-13
申请号：JP13034693
申请日：1993-06-01
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO
IPC分类号： G06F1/32 , G06F9/46
摘要： PURPOSE:To reduce the power consumption by detecting an endless loop by using an idle state recognition start address and an idle state recognition end address. CONSTITUTION:The idle state recognition start address 2a and idle state recognition end address 2b can be set in a 1st register of an address coincidence detecting means 30. A 1st comparator 7 compares the address stored in this register with an address stored in a program counter 1. A period wherein an idle state is detected can be set in a 2nd register 9. A counter 8 counts variation of the detection signal from the address coincidence detecting means 30. A 2nd comparator 10 compares the contents of the 2nd register 9 with the contents of the counter 8. The detection signal from the 2nd comparator 10 is controlled to detect the idle state. Consequently, when a microprocessor is in the idle state for a certain time, its power supply can be stopped.

18. 发明专利

JPH05204643A INFORMATION PROCESSOR 失效
公开(公告)号：JPH05204643A
公开(公告)日：1993-08-13
申请号：JP1518292
申请日：1992-01-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO
IPC分类号： G06F9/38
摘要： PURPOSE:To provide an information processor capable of simultaneously executing plural instructions generating register interference. CONSTITUTION:Two instructions respectively stored in instruction queues C, D so as to be executed next are previously read out by prereading decoders 38, 39 and executed by preceding arithmetic processors 54, 55 and their executed results are stored in storage means 62, 63. Then these instructions are read out by a decoder 3 through instruction queues A, B and executed by the 1st and 2nd arithmetic processors 5, 6. When the generation of register interference between the two instructions is detected by the 1st and 2nd comparators 66, 67, the processed results stored in the means 62, 63 are used as the source data of one of the instructions generating the register interference.

19. 发明专利

JPH03257847A METHOD OF VERIFYING LAYOUT 失效
公开(公告)号：JPH03257847A
公开(公告)日：1991-11-18
申请号：JP5531090
申请日：1990-03-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIUMI NORIO , TAKAGI YOSHIYUKI
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/04
摘要： PURPOSE:To make it possible to detect the source of a transistor having no feed from a wiring for feeding a power supply potential or a ground potential by subtracting the graphical data, which corresponds to the connections between the wiring for feeding a power supply potential or a ground potential and a substrate, from the graphical data of a semiconductor integrated circuit and by extracting the information for connecting transistors with each other and by performing electrical rule checking and connection collation. CONSTITUTION:Graphical data of P diffusions 9, 10 are subtracted from the graphical data of a semiconductor integrated circuit. The information for connecting transistors with each other are extracted from the graphical data of the semiconductor integrated circuit after completing its processings. At this time, a ground potential is given directly to an N diffusion 2 for the source of a transistor through a wiring 8 for feeding a ground potential. Since the wiring 8 for feeding a ground potential is disconnected at a point A, an N diffusion 4 for the source of another transistor hasn't the ground potential. Electrical rule checking(ERC) is performed for the information for connecting transistors with each other after completing their processings. Then, the source 4 of the N channel transistor having no ground potential is detected as an error.

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