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11. 发明专利

JPS5585950A SPEED CONVERSION RECEPTION UNIT FOR SERIAL MULTIISIGNAL 失效
公开(公告)号：JPS5585950A
公开(公告)日：1980-06-28
申请号：JP16378978
申请日：1978-12-21
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NODA SHIYUNEI , HARADA YOSHIHISA , UNEMURA TOYOAKI
IPC分类号： H03M9/00 , G06F13/00 , H04L13/08
摘要： PURPOSE:To efficiently perform the reception processing of versatile serial signals, by storing the serial input signal at reception to the memory element in serial input and parallel output and reading out the parallel signal output as the serial signal at readout. CONSTITUTION:The information processor 9 outputs the selection signals 8, 14, 21 respectively to the selection circuit 3, clock selection circuit 13, and mode selection circuit 20, for the selection in matching with the signal desired to be received for the reception data 11-1N and the clock signals 21-2N corresponding to them. The reception data 1 selected at the circuit 3 is fed to the shift register 23 and converted into parallel signal. The output signals 241, 242 of the register 23 are stored in the memory elements 291, 292 via the latch registers 271, 272. At readout, the output of the elements 291, 292 are fed to the register 23 as the serial signal outputs 301, 302 and stored in the elements 291, 292 again via the latches 271, 272. The unit 9 reads out the output signal 241 converted into serial signal taking timing for the internal clock signal 12.

12. 发明专利

JPS5577787A DISPLAY UNIT 失效
公开(公告)号：JPS5577787A
公开(公告)日：1980-06-11
申请号：JP15236278
申请日：1978-12-08
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HARADA YOSHIHISA , NODA SHIYUNEI , UNEMURA TOYOAKI
IPC分类号： G09G5/395 , G09G1/14 , G09G5/02

13. 发明专利

JPS5532300A REPRODUCING UNIT 失效
公开(公告)号：JPS5532300A
公开(公告)日：1980-03-06
申请号：JP10646979
申请日：1979-08-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： IRIMICHI TOMOAKI , IZUMI HIROSHI , KATAHIRA TOSHIAKI , YUKANAMI YUKIO , HARADA YOSHIHISA
IPC分类号： H04N5/92 , G11B5/02 , G11B20/02
摘要： PURPOSE:To reduce the memory capacity for sampling, by avoiding recording for a plurality of times for the compressed signal and the synchronizing signal during one revolution of magnetic sheet. CONSTITUTION:The capacitor memory 2 stores the input signals such as audio sectioned into (mn-4) via the low speed counter 13 of the control circuit 4. (where ; m, n are integers respectively 2,3 or more.) The memory content of the memory 2 is read out in the speed of 1/n at write-in via the high speed counter and it is converted into the compressed signal, and it is further synthesized with the synchronizing signal produced from the synchronizing signal generator circuit 17 through the counter 12. The synthesized signal is sequentially and intermittently recorded at the area in (mn-1) equal division for circumference of the magnetic sheet 6 in the rate of m times per one revolution of the sheet 6. With the system of absence of recording for a plurality of times during one revolution of the recording medium, the number of samples is decreased to enable reduce the storage capacity of the memory 2. This is the same for reproduction of signal expansion.

14. 发明专利

JPS5165911A Kirokusochi oyobi saiseisochi 失效
公开(公告)号：JPS5165911A
公开(公告)日：1976-06-08
申请号：JP13974974
申请日：1974-12-04
申请人： Matsushita Electric Ind Co Ltd
发明人： IRIMICHI TOMOAKI , HARADA YOSHIHISA , KATAHIRA TOSHIAKI
IPC分类号： G11B20/02 , G11B5/012 , G11B5/09 , H04N5/78 , H04N5/928

15. 发明专利

JPS5165857A Kondensa memori 失效
公开(公告)号：JPS5165857A
公开(公告)日：1976-06-07
申请号：JP13975574
申请日：1974-12-04
申请人： Matsushita Electric Ind Co Ltd
发明人： IRIMICHI TOMOAKI , IZUMI HIROSHI , KATAHIRA TOSHIAKI , TOKONAMI IKUO , HARADA YOSHIHISA
IPC分类号： G11C11/56 , G11C11/24 , G11C27/00

16. 发明专利

JP2006173320A Semiconductor device having field effect transistor equipped with high dielectric constant gate insulating film and its manufacturing method 有权
标题翻译：具有高介电常数绝缘膜的场效应晶体管的半导体器件及其制造方法
公开(公告)号：JP2006173320A
公开(公告)日：2006-06-29
申请号：JP2004362971
申请日：2004-12-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HARADA YOSHIHISA , HAYASHI SHIGENORI , NIWA MASAAKI
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/786
CPC分类号： H01L21/28229 , H01L21/28185 , H01L21/823807 , H01L21/823814 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To improve the controllability of a threshold voltage in an FET using a high dielectric constant gate insulating film, and in its manufacturing method.
SOLUTION: After a high dielectric constant gate insulating film 110 is formed on a substrate 101, a gate electrode 111a is formed on the high dielectric constant gate insulating film 110. Then, an n-type impurity is introduced into the substrate 101 by taking at least the gate electrode 111a as a mask to form an n-type extension region 113. Subsequently, a p-type impurity is introduced below the n-type extension region 113 on the substrate 101 by taking at least the gate electrode 111a as a mask to form a p-type pocket region 114. Herein, an introduction amount of arsenic (As) as the n-type impurity into the n-type extension region 113 is set within a certain range of a predetermined value or lower defined on the basis of the thickness of the high dielectric constant gate insulating film 110.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提高使用高介电常数栅极绝缘膜的FET中的阈值电压的可控性，以及其制造方法。解决方案：在基板101上形成高介电常数栅极绝缘膜110之后，在高介电常数栅极绝缘膜110上形成栅电极111a。然后，将n型杂质引入到基板101中通过至少将栅电极111a作为掩模形成n型延伸区域113.随后，通过至少选择栅电极111a将p型杂质引入到衬底101上的n型延伸区域113的下方作为形成p型袋区域114的掩模。这里，将作为n型杂质的砷（As）作为n型延伸区域113的导入量设定在规定值以下的一定范围内基于高介电常数栅极绝缘膜110的厚度。版权所有（C）2006，JPO＆NCIPI

17. 发明专利

JP2006121090A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006121090A
公开(公告)日：2006-05-11
申请号：JP2005304756
申请日：2005-10-19
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HARADA YOSHIHISA
IPC分类号： H01L21/316 , C23C16/56 , H01L21/283 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a high-k gate insulating film excellent in thermal stability.
SOLUTION: A high-k film 14 of HfO2 is deposited on a substrate 11 using a CVD method. Then, a gate electrode 15 is formed on the high-k film 14. Then, an activate annealing treatment to an impurity poured into a source/drain region or the gate electrode 15 is carried out. When the deposition temperature of the high-k film 14 is set to x [°C] and the temperature of the activate annealing treatment is set to y [°C], x and y satisfy y≤0.5×x+825.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供热稳定性优异的高k栅绝缘膜。解决方案：使用CVD法将HfO 2的高k膜14沉积在基板11上。然后，在高k膜14上形成栅电极15.然后，对流入源/漏区或栅极15的杂质进行活化退火处理。当高k膜14的沉积温度设定为x [℃]，活化退火处理的温度设定为y [℃]时，x和y满足y≤0.5×x + 825。版权所有（C）2006，JPO＆NCIPI

18. 发明专利

JP2003059926A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2003059926A
公开(公告)日：2003-02-28
申请号：JP2002163983
申请日：2002-06-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HARADA YOSHIHISA
IPC分类号： H01L21/318 , H01L21/316 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a high-k gate insulation film having a long reliability life.
SOLUTION: The high-k gate insulation film formed between an Si substrate 11 and a gate electrode 17 comprises an interface layer 15 formed on an interface with the Si substrate 11, and a high-k layer 16 which is formed on the interface layer 15 and has a high relative permittivity than that of the interface layer 15. The thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 should satisfy T1/(T1+T2)≤0.3, or more preferably, T1/(T1+T2)≤0.2.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供具有长的可靠性寿命的高k栅绝缘膜。解决方案：形成在Si衬底11和栅电极17之间的高k栅极绝缘膜包括形成在与Si衬底11的界面上的界面层15和形成在界面层15上的高k层16 并且具有比界面层15高的相对介电常数。界面层15的厚度T1和高k层16的厚度T2应满足T1 /（T1 + T2）≤0.3，或者更优选地， T1 /（T1 + T2）<= 0.2。

19. 发明专利

JP2000269177A CLEANING METHOD OF SEMICONDUCTOR 失效
公开(公告)号：JP2000269177A
公开(公告)日：2000-09-29
申请号：JP7474999
申请日：1999-03-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HARADA YOSHIHISA , NIWA MASAAKI
IPC分类号： B08B3/08 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To reduce iron concentration and carbon contamination of a substance surface and thereby to improve reliability, in SC-1 cleaning used for cleaning of a semiconductor substrate. SOLUTION: This method comprises a process of cleaning the surface of a semiconductor substrate by a semiconductor surface treating agent, of which the constituents are alkali, hydrogen peroxide and water and a process of rinsing the surface of the semiconductor substrate with ultrapure water after the cleaning, and a cleaning chemical to which a complexing agent containing one or more phosphonic acid group or salts thereof in the molecule is added in the range of 2.1E-5 to 4.2E-5 wt.% is used for at least one of the semiconductor surface treating agent and the ultrapure water for rinsing. According to this constitution, an improvement in reliability can be expected from the effect of removal of iron by the complexing agent, and moreover, lowering of the reliability due to carbon contamination is lessened. Therefore a cumulative fraction defective is made small, and improvement in the reliability can be realized in particular. Furthermore, reliability is improved, with regard to other chemicals and complexing agents, by providing the concentration of the complexing agent to be set within the range of 0.9-1.8 times that at the saturation temperature thereof.

20. 发明专利

JPH11224872A SURFACE TREATMENT METHOD FOR SILICON 失效
公开(公告)号：JPH11224872A
公开(公告)日：1999-08-17
申请号：JP2337998
申请日：1998-02-04
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HARADA YOSHIHISA
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To surely and efficiently form a clean surface of silicon. SOLUTION: A silicon clean surface is formed by vacuum heating a silicon substrate 5, where an oxidized film 4 provided with a film thickness of 1 nm or larger and 2 nm or smaller is present on the surface. Since the silicon clean surface is formed by vacuum heating the silicon substrate 5, where the oxidized film 4 provided with a film thickness of 1 nm or lager is present on the surface, the physical or chemical bonding to an active silicon surface and carbon in gas is restrained and carbon 3 is almost all removed. Also since the time required for reaction for sublimating the oxidized film 4 increases along with the increase of an oxidized film thickness, when the oxidized film 4 become thick, it takes more than the required time for oxidized film removal reaction in a vacuum and becomes inefficient. However, since the film thickness of the oxidized film 4 is set to be 1 nm or larger and 2 nm or smaller, the carbon is sufficiently removed and processing time is shortened. Thus, a clean silicon surface for not generating Si-C bonding is formed surely and efficiently.

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