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11. 发明专利

JPS5534508A MULTIIFREQUENCY SIGNAL RECEIVER 失效
公开(公告)号：JPS5534508A
公开(公告)日：1980-03-11
申请号：JP10621778
申请日：1978-09-01
申请人： HITACHI LTD
发明人： HIROSE KAZUTO , HASHIDA MITSUYOSHI
IPC分类号： H04L27/26 , H04Q1/457
摘要： PURPOSE:To obtain an economical logic circuit of the receiver which prevents the malfunction caused by the noise by shortening the action recovery time for the signal detection and making insensitive the recovery due to the signal short break after detection for the digital multi-frequency signal receiver using the discrete Fourier conversion. CONSTITUTION:Block A is the arithmetic part of tone spectrum intensity DFT, and the output logic part is shown by C. The output given from arithmetic output DFT is supplied to comparator 14 via PCM to be compared with the threshold level stored into register 15. And the output exceeding the threshold level is latched by shift register 23 in the form of logic 1. Receiver output SP is calculated through accumulators (30, 31) comprising the recovery time, and latch gate 29 is opened to FF1 when the signal specturm exists to shorten the recovery time. The threshold level set to register 33 is selected to secure the insensitivity for the short break. As the gate control is given to the reception information output with the SP value of the sum of DFT (omeganu) against the noise, the insensitivity is secured for the signals outside the band.

12. 发明专利

JPS54104216A RECEIVER FOR DIGITAL MULTIIFREQUENCY SIGNAL 失效
公开(公告)号：JPS54104216A
公开(公告)日：1979-08-16
申请号：JP1057278
申请日：1978-02-03
申请人： HITACHI LTD
发明人： HASHIDA MITSUYOSHI , HIROSE KAZUTO
IPC分类号： H04Q1/457 , H04L27/26
摘要： PURPOSE:To simplify the circuit constitution of a receiver which uses a discrete Fourier transforming method by making the circuit into costitution for eight-wave processing and by attaining the multiplication of a window function and square-law multiplication for power making use of a free time for two waves at the time of the matching of a clock speed with a time-division switchboard. CONSTITUTION:Thr receiver which receives and processes a multi-frequency signal after pulse-code modulation using a discrete Fourier transforming method is equipped with two arithmetic units which have multipliers 6 and 7, adders 8 and 9, delay memories 10 and 11, absolute-value circuits 12 and 13 as integrating circuits respectively. Further, one common read-only memory ROM 22 for both arithmetic units is provided, and both groups are equipped with shift registers 23 and 24 of 16-bit word length. Then, a window function read out from ROM 22 by the multiple use of memories 10 and 11 is multiplied by input data and its result is held temporarily and squared; and sine and consine values read out from ROM 22 are multiplied by corresponding multiplication results, and logic circuit 15 finds the absolute- value or square-law sum via circuit 12 or 13.

13. 发明专利

JPH06324876A OBJECT INFORMATION DEFINITION SUPPORTING SYSTEM 失效
公开(公告)号：JPH06324876A
公开(公告)日：1994-11-25
申请号：JP11430893
申请日：1993-05-17
申请人： HITACHI LTD , HITACHI CHUBU SOFTWARE KK
发明人： NAGAI YASUHIKO , SUZUKI MICHIO , SUGAUCHI KIMITOKU , SUZUKI HIROTOMO , SAITO MASATO , HASHIDA MITSUYOSHI
IPC分类号： G06F9/44 , G06F9/06 , G06F12/00 , G06F13/00 , G06F17/30 , G06F15/40
摘要： PURPOSE:To efficiently support the registration and operating processing of standard class information by a system in which object class information made into standard and common use under decentralized environment can be semi-automatically generated and updated. CONSTITUTION:The support of the registration and operating processing of the standard class information can be attained by plural definition input devices 102 which input the feature information of a definition target, program memory 114 in which a program group to semi-automatically generate and update the class information based on definition communication protocol processing 107 to collect a feature information group from the definition input device and collected feature information is stored, and one registration managing device 101 which performs the unitary management of the generation and update of the standard class information by a data base 104 in which the feature information and generated class information are stored. Thereby, it is possible to provide an information management supporting system in which the class information can be accurately generated in detail in the registration and the operation of the standard object class information under the decentralized environment, and definition work time can be efficiently used, and defining burden on a person can be reduced, and the comprehensive management of the standard class information can be performed.

14. 发明专利

JPH05130026A PORTABLE TELEPHONE SYSTEM 失效
公开(公告)号：JPH05130026A
公开(公告)日：1993-05-25
申请号：JP29268591
申请日：1991-11-08
申请人： HITACHI LTD
发明人： HASHIDA MITSUYOSHI , ITO FUMITAKA , WATABE YUMIKO
IPC分类号： H04B7/26 , H04W48/20 , H04W88/02
摘要： PURPOSE:To improve the convenience of the portable set for the user of the portable telephone system. CONSTITUTION:The portable set is provided with a means 11 connecting to an indoor use base station in a radio wave and a means 12 connecting to an outdoor use base station in a radio wave and both of them are available of connection. In this case, the portable set is provided with a display means 18 displaying a state of a transmission line to be connected and the means 18 displays information 181 for an outgoing path and information 183 for an incoming call path and selects the path. One package of the telephone set is enough to make communication for an outdoor and an indoor base station by having an indoor use radio section 11 and an outdoor use radio section 12.

15. 发明专利

JPH01128561A LOGIC LSI 失效
公开(公告)号：JPH01128561A
公开(公告)日：1989-05-22
申请号：JP28536087
申请日：1987-11-13
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HASHIDA MITSUYOSHI , KOSUGI NORITAKA , KAJIKAWA TAKANOBU , ARITA KAORU
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PURPOSE:To set the state of the pins of a LSI uniformly irrespective of the internal logic of the LSI and to reduce a time and a cost consumed for a DC parameter test by composing an input/output buffer of input/output buffer cell having a control function capable of setting the state of input/output pins irrespective of the internal logic. CONSTITUTION:Two control input pins 11, 12, a control input buffer 101 having the control function of logic signal pins 21 and input/output buffer 1 are provided thereby to uniformly fix the states of the pins 21 and to set as the logic signal pin of a normal mode. An output only pin can set by two control inputs 3 output states (internal signal outputs of a low level output 'L', a high level output 'H' and a normal logic mode) can be set, and a bus pin having a tristate buffer can set 4 output states (high impedance output 'Z' state is added to the above 3 output states).

16. 发明专利

JPS61142474A Aging apparatus with power source cutting function 失效
标题翻译：具有电源切割功能的老化设备
公开(公告)号：JPS61142474A
公开(公告)日：1986-06-30
申请号：JP26445284
申请日：1984-12-17
申请人： Hitachi Ltd
发明人： HASHIDA MITSUYOSHI
IPC分类号： G01R31/26 , H01L21/66
摘要： PURPOSE: To achieve a higher reliability, by providing a power source cutting circuit comprising a monitor circuit and a switch circuit on a boat for mounting an object to be aged to secure a protecting function against abnormality in the power source during the aging.
CONSTITUTION: An aging apparatus is equipped with a monitor circuit 5 for detecting a drop in the power source and a power source cutting circuit 4 comprising switch circuits 61 and 62 to be controlled by the output thereof on a boat 2 for mounting an object to be aged. In this case, as transistors Q
2 and Q
3 of the switch circuits 61 and 62 are turned ON by output current of a transistor Q
1 of the power source voltage monitoring circuit 5, voltages of other power sources 12 and 13 are applied to the object being aged as intact through the switch circuits 61 and 62 with power source wires (b) and (c). But when the maximum potential of a power source 11 falls below the Zener voltage of a Zener diode DZ, the output current of the transistor Q
1 fails to flow to turn OFF the transistors Q
2 and Q
3 and causes the power sources 11 and 12 to be cut to secure a protecting function thereby elevating the reliability.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了达到更高的可靠性，通过提供一种电源切割电路，该电源切割电路包括在船上的监视电路和开关电路，用于安装老化对象以确保在老化期间电源中的异常的保护功能。构成：老化装置配备有用于检测电源的下降的监视电路5以及电源切断电路4，电源切断电路4由切换电路61,62控制，该电路切换电路由其输出控制在用于安装物体的船2上年龄在这种情况下，由于开关电路61和62的晶体管Q2和Q3通过电源电压监视电路5的晶体管Q1的输出电流导通，其他电源12和13的电压被施加到被老化的对象通过具有电源线（b）和（c）的开关电路61和62完整。但是当电源11的最大电位下降到齐纳二极管DZ的齐纳电压以下时，晶体管Q1的输出电流不能流过，从而使晶体管Q2和Q3截止，导致电源11和12被切断以确保保护功能从而提高可靠性。

17. 发明专利

JPS60150662A SEMICONDUCTOR INTEGRATED LOGIC DEVICE 失效
公开(公告)号：JPS60150662A
公开(公告)日：1985-08-08
申请号：JP559484
申请日：1984-01-18
申请人： HITACHI LTD
发明人： HASHIDA MITSUYOSHI
IPC分类号： H01L21/822 , H01L27/04
摘要： PURPOSE:To simplify the control of input-output cells, to reduce man-hours for preparing a pattern and to shorten testing time by adopting constitution separately mounted to an internal logic as an input-output cell control function. CONSTITUTION:An input-output cell control cell is connected to one or more of input-output cells 2 on the outside of a region containing a logic circuit, and controls the state of the input-output cells 2. When the input-output cells 2 are tested, the input-output cells 2 can be set to a desired state by bringing a terminal S to a ''1'' level and a terminal D1 to a ''0'' level and bringing a terminal D0 to a ''0'' or ''1'' level. Methods in which the structure, number and arrangement of the input-output cell control cells 3 and the ways of connection to the input- output cells 2 are arbitrary are adopted except a method in which one input- output cell control cell 3 is disposed at the center of an upper side and connected to all input-output cells 2. Input data to the input-output cell control cell 3 may be inputted through an internal logic circuit except direct input from a package pin.

18. 发明专利

JPS57118425A Digital pattern generating circuit 失效
标题翻译：数字图案发生电路
公开(公告)号：JPS57118425A
公开(公告)日：1982-07-23
申请号：JP305081
申请日：1981-01-14
申请人： Hitachi Ltd
发明人： HASHIDA MITSUYOSHI
IPC分类号： H03K3/78
CPC分类号： H03K3/78
摘要： PURPOSE:To decrease the number of shift registers, by using a shift register in common and a set pattern to the shift register after switching the pattern. CONSTITUTION:In case a data input D1 of ''1'' is applied at a time point when the load input is set at L1, 00000101 is supplied to input terminals IA-IH of a shift register 3. The above-mentioned data set to these input terminals are successively read after a shift carried out by the clock signal. Thus serial data output of 10100000 is obtained through an output terminal OUT. When data input D2 of ''0'' is applied at a time point when the load input is set at L2, data of 00010011 is supplied to the input terminals IA-IH. This data is read after being shifted by the clock signal to obtain serial data of 11001000 through the terminal OUT. In other words, the function equivalent to two shift registers can be obtained by a shift register with use of loads L1 and L2 plus data D1 and D2.
摘要翻译：目的：为了减少移位寄存器的数量，在切换模式后，通过使用公共端的移位寄存器和移位寄存器的设置模式。构成：如果在负载输入被设置为L1的时间点应用“1”的数据输入D1，则将00000101提供给移位寄存器3的输入端子IA-IH。上述数据组在由时钟信号进行的移位之后连续地读取这些输入端。因此，通过输出端子OUT获得10100000的串行数据输出。当在负载输入设置为L2的时间点应用“0”的数据输入D2时，00010011的数据被提供给输入端子IA-1H。在通过时钟信号移位后读取该数据，通过端子OUT获得11001000的串行数据。换句话说，等效于两个移位寄存器的功能可以通过使用负载L1和L2加上数据D1和D2的移位寄存器来获得。

19. 发明专利

JPS57115019A CLOCK PULSE CONVERTING SYSTEM 失效
公开(公告)号：JPS57115019A
公开(公告)日：1982-07-17
申请号：JP112081
申请日：1981-01-09
申请人： HITACHI LTD
发明人： HASHIDA MITSUYOSHI
IPC分类号： H03K5/00 , G06F7/68
摘要： PURPOSE:To achieve rate conversion between pulses with different rate, by mixing an input pulse itself with frequency-divided or multiplied input pulse for a specified amount. CONSTITUTION:A frequency-division/multiplication circuit 2 outputs a pulse of no-conversion from a terminal TH, pulse of 1/2 frequency-division from a terminal DV, and doubled pulse from a terminal MP. To convert a pulse CP1 in clock rate f1 (2.048MHz) into a pulse in clock rate f2 (l.554MHz), 63 pulses in l.024MHz outputted from the terminal DV are transmitted through a selector 3, the selector 3 is switched by a D type FF5, and 130 pulses in 2.048MHz outputted from the terminal TH are transmitted through the selector 3. To convert the pulse in rate f2 into a pulse in rate f1, the output pulses at the terminals MP and TH are mixed similarly.

20. 发明专利

JPH07312773A PORTABLE TELEPHONE SYSTEM 失效
公开(公告)号：JPH07312773A
公开(公告)日：1995-11-28
申请号：JP15901394
申请日：1994-07-11
申请人： HITACHI LTD , KOKUSAI ELECTRIC CO LTD
发明人： FUKUSHIMA YUTAKA , TAKEMURA TETSUO , IWAKI SHINICHI , HASHIDA MITSUYOSHI , WANAMI MASAO , SHINPO ISAO , WADA MITSUHIRO , UTAKI HIROSHI , KONDOU YOSHIHIRO , YAMAMOTO YOSHINOBU , NAKAKOSHI ARATA , WATABE YUMIKO , OTA KOICHI , KUWABARA HIROSHI
IPC分类号： H04B10/00 , H04B10/032 , H04B10/2507 , H04B10/272 , H04W56/00 , H04W76/02 , H04W84/10 , H04W88/14 , H04W92/00 , H04Q7/22 , H04Q7/24 , H04Q7/26 , H04Q7/30 , H04Q7/38
摘要： PURPOSE:To prevent the interference among radio base stations without the provision of a special physical transmission line and to improve the reliability of the system. CONSTITUTION:A base station controller 3 and a radio base station 2 as to each system are interconnected by optical fibers in duplicate. The optical fibers in duplicate are connected to each radio base station 2 of a concerned system via a star coupler. Then each radio base station 2 is arranged to each zone so that radio base stations of different systems are adjacent to each other. The interface between the base station controller 3 and the radio base station 2 is an I interface and each radio base station 2 makes ping-pong transmission with a portable telephone set synchronously with a multi-frame built in the I interface.

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