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1. 发明专利

JPH01128561A LOGIC LSI 失效
公开(公告)号：JPH01128561A
公开(公告)日：1989-05-22
申请号：JP28536087
申请日：1987-11-13
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HASHIDA MITSUYOSHI , KOSUGI NORITAKA , KAJIKAWA TAKANOBU , ARITA KAORU
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PURPOSE:To set the state of the pins of a LSI uniformly irrespective of the internal logic of the LSI and to reduce a time and a cost consumed for a DC parameter test by composing an input/output buffer of input/output buffer cell having a control function capable of setting the state of input/output pins irrespective of the internal logic. CONSTITUTION:Two control input pins 11, 12, a control input buffer 101 having the control function of logic signal pins 21 and input/output buffer 1 are provided thereby to uniformly fix the states of the pins 21 and to set as the logic signal pin of a normal mode. An output only pin can set by two control inputs 3 output states (internal signal outputs of a low level output 'L', a high level output 'H' and a normal logic mode) can be set, and a bus pin having a tristate buffer can set 4 output states (high impedance output 'Z' state is added to the above 3 output states).

2. 发明专利

JP2000347764A METHOD FOR CONNECTING CIRCUIT BLOCK USING PLL AND METHOD FOR CONNECTING SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2000347764A
公开(公告)日：2000-12-15
申请号：JP16055699
申请日：1999-06-08
申请人： HITACHI LTD
发明人： NOMURA HIROSHI , KOSUGI NORITAKA , TONOZUKA TAROU , YOKOTA MITSUKUNI , HIRANO KATSUNORI , NAGASAKI FUMIHIKO
IPC分类号： G06F1/10 , H03L7/06 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To reduce the variation of delay fluctuations of LSI output data caused by LSI process variation, power supply voltage fluctuations, ambient temperature change or the like. SOLUTION: A feedback path to a PLL inputting part consists of a clock distribution circuit 11, a PLL feedback clock output buffer 21, a PLL feedback loop wiring 22 and a PLL feedback clock input buffer 20, and meanwhile, a data transfer path consists of a data output buffer 8 which is synchronized with a clock outputted from the circuit 11 and outputs it to an LSI on the next stage and a data wiring 14 which transfers data to the LSI on the next stage.

3. 发明专利

JPH10221409A FIELD PROGRAMMABLE GATE ARRAY 失效
公开(公告)号：JPH10221409A
公开(公告)日：1998-08-21
申请号：JP2238697
申请日：1997-02-05
申请人： HITACHI LTD
发明人： KOSUGI NORITAKA
IPC分类号： G01R31/317 , G01R31/28 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/173
摘要： PROBLEM TO BE SOLVED: To generate a test pattern automatically in normal operation logic by providing select gates for test at the output part of a macrocell FF and the input part of a combination circuit part. SOLUTION: Logic values are set for all macrocells with a 1 clock by providing a select gate for test at the output part of a macrocell FF 12 and the input part of a combination circuit part 10 along with a data wiring for test fixed in view point of hardware. More specifically, the test data at the combination circuit part 10 can be set at an arbitrary value from a test data testd5 thereat by bringing a data select signal tselm6 into '1' state. The test data of the FF12 can be set at an arbitrary value from tdi1 by bringing a data select signal tself7 of the FF12 into '1' state. Furthermore, the FF12 reads out an expected output from the combination circuit part 10.

4. 发明专利

JPH03211912A D TYPE FLIP-FLOP 失效
公开(公告)号：JPH03211912A
公开(公告)日：1991-09-17
申请号：JP617590
申请日：1990-01-17
申请人： HITACHI LTD
发明人： KOSUGI NORITAKA
IPC分类号： H03K3/037
摘要： PURPOSE:To input external data only at the time when a specific condition is formed, and to prevent the malfunction caused by a logical hazard of a CK signal by providing a selection gate for selecting the data as to whether the current own data is held in a data terminal, or the data from the outside is inputted. CONSTITUTION:A positive edge D type flip-flop containing a 2-1 selector circuit constituted of an inverter 1, NAND gates 2, 3 and a NOR gate 4 is constituted, and as for a CK signal 10, in order to adjust a delay time to the 2-1 selector circuit, delay adjusting inverters 8, 9 are inserted. In the case of inputting the data under a specific condition, an edge trigger D type flip-flop switches a selecting signal to an external data selection mode at the time when its condition is formed. In such a way, only at the time of the specific condition, external data can be inputted, and a logical operation of the CK signal becomes unnecessary, therefore, it does not occur that the edge trigger D type flip-flop causes a malfunction by a logical hazard of the CK signal.

5. 发明专利

JPH1155374A ELECTRONIC EQUIPMENT 失效
公开(公告)号：JPH1155374A
公开(公告)日：1999-02-26
申请号：JP16943798
申请日：1998-06-17
申请人： HITACHI LTD
发明人： YAMANA YOSHIYUKI , FURUYA JUN , MATSUMOTO KUNIO , KAMIMURA OSAMU , KOSUGI NORITAKA , NAKAGAWA JUNICHI
IPC分类号： G06K17/00 , H04M1/02
摘要： PROBLEM TO BE SOLVED: To provide an electronic equipment in which a space for mounting a magnetic card can be reduced. SOLUTION: This device (for example, a portable telephone) is provided with a main body 4 and a battery pack 2 connectable with and separatable from the main body 4. In a state that the main body 4 is connected with the battery pack 2, a housing space (c) for housing a magnetic card 1 is formed between faced outer wall faces 4a and 2a among each outer wall faces, and an opening (d) for inserting the magnetic card 1 into the housing space (c) is formed on the side face of the main body 4 and the battery pack 2. The main body 4 is provided with a magnetic card read head 3.

6. 发明专利

JPH05153217A MOUNTING METHOD FOR CARD 失效
公开(公告)号：JPH05153217A
公开(公告)日：1993-06-18
申请号：JP31496291
申请日：1991-11-28
申请人： HITACHI LTD
发明人： YAMANA YOSHIYUKI , FURUYA JUN , MATSUMOTO KUNIO , KAMIMURA OSAMU , KOSUGI NORITAKA , NAKAGAWA JUNICHI
IPC分类号： G06K17/00 , G06F17/40 , H04M1/02
摘要： PURPOSE:To provide a card mounting method with little mounting space. CONSTITUTION:An electronic device includes a first member 2 and a second member 3, which are integrated at the time of use and can be separated at the time of non-use. It has a card mounting means (c) holding a card 1 between the first member 2 and the second member 3 at the time of use. Thus, the mounting space of the IC card can be set to a minimum and the protection and the waterproofing of the IC card 1 can easily be attained.

7. 发明专利

JP2001007776A LOW POWER CONSUMPTION SDH LAYER TERMINATING CIRCUIT 失效
公开(公告)号：JP2001007776A
公开(公告)日：2001-01-12
申请号：JP17602599
申请日：1999-06-22
申请人： HITACHI LTD
发明人： TONOZUKA TAROU , NOMURA HIROSHI , ITAGAKI TATSUYA , NAGASAKI FUMIHIKO , KOSUGI NORITAKA , KAWASAKI KAZUHIRO , NISHINO RYOSUKE
IPC分类号： H04J3/00
摘要： PROBLEM TO BE SOLVED: To provide an SDH layer terminating circuit for STM-N with less power consumption by providing a mask means for fixing the value of a count signal which is to be supplied to a timing signal generation circuit for a prescribed time. SOLUTION: A mask circuit 77 for masking frame counter output is inserted between an STM-1 frame counter generation circuit 36 and an SOH timing generating circuit 40. A mask signal generation circuit 78 generates a frame counter mask signal 80, based on counter outputs COL and CH outputted from the frame counter generation circuit 36. The mask signal 80 becomes a '0' state in the reception period of the payload part of an SDH frame. AND gates 81 and 82 output count values COLMSK and CHMSK, whose valued are fixed to '0' to the SOH timing generation circuit 40. Thus, power consumption with charging and discharging becomes '0' in a payload period.

8. 发明专利

JPH05211472A DIGITAL MOBILE BODY TERMINAL EQUIPMENT 失效
公开(公告)号：JPH05211472A
公开(公告)日：1993-08-20
申请号：JP1589892
申请日：1992-01-31
申请人： HITACHI LTD
发明人： KOSUGI NORITAKA , YAMANA YOSHIYUKI , FURUYA JUN , MATSUMOTO KUNIO , KAMIMURA OSAMU , NAKAGAWA JUNICHI
IPC分类号： H04B7/26 , H04W4/12 , H04W88/02
摘要： PURPOSE:To simply implement character call by a routine document while keeping the privacy. CONSTITUTION:Each of two or more digital mobile body terminals is provided with a routine document storage section 3 in which the same routine document is stored in the same address. A routine document to be sent is selected by a routine document selection section 1 and a routine document display section 5 at a sender side, and address information and error detection information of the selected routine document are transferred through a B.BLSI6, RF7 by using an information channel TCH of a radio channel. Error check is applied to the received data at the receiver side and the routine document corresponding to the address information is displayed on the routine document display section.

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