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11. 发明专利

JPS60253272A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60253272A
公开(公告)日：1985-12-13
申请号：JP10837284
申请日：1984-05-30
申请人： HITACHI LTD
发明人： SAKAI YOSHIO , MOTOYOSHI MAKOTO
IPC分类号： H01L29/78
摘要： PURPOSE:To reduce the resistance of source-drain, and to prevent the lowering of the mutual conductance of an MOSFET by forming a high-concentration impurity region having the same conduction type as source-drain to the lower section of a low-concentration impurity region for the source-drain. CONSTITUTION:In an MOSFET such as an N channel one, low-impurity N type diffusion layers 5 having depth of 0.3mum or less and impurity concentration of 16 -10 cm are shaped in regions being in contact with a gate electrode 2 in order to increase withstanding voltage between a source and a drain. Since a depletion layer extends from a P type substrate 1 in the regions, electric-field concentration at the end of the drain is relaxed, and the extension of the depletion layer contributes to the increase of withstanding voltage. Low-resistance N type regions 6 having impurity concentration of 10 cm or more are formed to the lower sections of the low concentration regions 5 in order to prevent the lowering of mutual conductance by the resistance of the low concentration regions 5.

12. 发明专利

JP2556673B2 失效
公开(公告)号：JP2556673B2
公开(公告)日：1996-11-20
申请号：JP29416894
申请日：1994-11-29
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/8244 , H01L27/11

13. 发明专利

JPS6432669A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6432669A
公开(公告)日：1989-02-02
申请号：JP18751787
申请日：1987-07-29
申请人： HITACHI LTD
发明人： YAMANAKA TOSHIAKI , SAKAI YOSHIO , MEGURO SATOSHI , SASAKI KATSURO , MOTOYOSHI MAKOTO
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8244 , H01L27/08 , H01L27/10 , H01L27/11
摘要： PURPOSE:To prevent the deterioration of the characteristics of an active MOS transistor and an element isolation section parasitic MOS transistor by obviating ion implantation into an electrode hole in a source impurity region in a drive MOS transistor by suing an ion implantation stopping film. CONSTITUTION:P-type wells are formed into an N-type silicon substrate 1, P-type channel stoppers 4' and silicon oxide films 4 for element isolation are shaped, and gate oxide films 10 are formed. Connecting holes 12b and gate electrodes 11a, 11b are shaped, and N-type impurity regions 9a, 9b, 3b, 3d, 3e are formed, employing the gate electrodes as masks for ion implantation. An silicon oxide film 5 is deposited, and high-resistance polycrystalline silicon films 17a, 17b are shaped. Connecting holes 13a, 13b, 13e are bored. A resist pattern 33 is formed, and the N-type impurity diffusion layers 9a, 9b are formed, using the resist pattern 33 as a mask for ion implantation.

14. 发明专利

JPS6246571A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6246571A
公开(公告)日：1987-02-28
申请号：JP18571985
申请日：1985-08-26
申请人： HITACHI LTD
发明人： SASAKI KATSUTO , IKEDA SHUJI , MOTOYOSHI MAKOTO
IPC分类号： H01L29/06 , H01L27/06 , H01L29/78
摘要： PURPOSE:To increase the electrostatic breakdown withstanding voltage of an element without inhibiting the fining of the element by thinly forming a reverse conduction type layer just under source-drain regions in a MOS type field-effect transistor. CONSTITUTION:An element region is demarcated by a field insulating film 2 on the surface of an N-type semiconductor substrate 1,and P-type well 3 having a conduction type reverse to the substrate 1 is shaped into the element region. The depth of the P-type well 3 is shaped in size thinner than other sections at a position 3a just under a drain region 7. Accordingly, punch-through withstanding voltage among source-drain regions and the substrate is lowered, and high electrostatic voltage applied to the source-drain regions can be made to escape instantaneously to the substrate, thus preventing the generation of high currents in a gate and between a source and a drain, then increasing the electrostatic withstanding voltage of an element.

15. 发明专利

JPS61182254A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61182254A
公开(公告)日：1986-08-14
申请号：JP2167385
申请日：1985-02-08
申请人： HITACHI LTD
发明人： IKEDA SHUJI , MOTOYOSHI MAKOTO
IPC分类号： H01L21/8234 , H01L21/22 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78
摘要： PURPOSE:To increase the speed of operation of an IC device by forming a diffusion preventive film in a connecting section between a semiconductor region and a conductive layer and inhibiting the augmentation of a resistance value in the connecting section. CONSTITUTION:An n well 2 is shaped to a p -Si substrate 1, thus forming CMOSFET's Qn, Qp. Thermal oxide films approximately 10nm thick are shaped onto n layers 7 and p layers 8 in connecting hole 10 sections, thus forming diffusion preventive films 11. P ions are implanted only to the n layers 7 in approximately 5X10 /cm at 50KeV through the films 11. The damage of the surfaces of the layers 7 is inhibited by the films 11. Deep n layers 12 approximately 0.5mum thick are shaped through an extension diffusion. The films 11 prevents the egress and ingress of an impurity to the layers 7, 8 during the extension diffusion, inhibits the lowering of the concentration of connecting sections with Al 13, and can bring a resistance value to a low value such as approximately 30OMEGA/mum . Accordingly, the speed of operation of an IC can be increased.

16. 发明专利

JPS61125166A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61125166A
公开(公告)日：1986-06-12
申请号：JP24602884
申请日：1984-11-22
申请人： Hitachi Ltd
发明人： IKEDA SHUJI , NAGASAWA KOICHI , MOTOYOSHI MAKOTO , NAGAI KIYOSHI , MEGURO SATOSHI
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823814 , H01L27/0928
摘要： PURPOSE:To prevent the generation of an alloy spike without increasing manufacturing processes by forming a contact hole for a CMOS device and introducing an N type impurity through the contact hole in concentration lower than a P type impurity layer. CONSTITUTION:A P type well 3 and an N type well 4 are formed onto a substrate 1 consisting of an N type silicon single crystal, a field insulating film 2 and a gate insulating film 21 are shaped, and gate electrodes 7, 11 and polycrystalline silicon films 14, 15 for wirings are formed. N type source-drain regions 8 and P type source-drain regions 12 are shaped, and an inter-layer insulating film 16 and a polycrystalline silicon film 17 are formed. Contact holes 22-26 are shaped, and N type impurity ions are implated to the whole surface in the quantity of low concentration, thus forming an impurity layer 9 having a deep junction. Al wirings are shaped, thus forming a CMOS type semiconductor device.
摘要翻译：目的：为了防止在不增加制造工艺的情况下产生合金尖峰，通过形成用于CMOS器件的接触孔并且通过接触孔以低于P型杂质层的浓度引入N型杂质。构成：在由N型硅单晶，场绝缘膜2和栅极绝缘膜21构成的基板1上形成AP型阱3和N型阱4，形成栅电极7,11和多晶硅形成用于布线的薄膜14,15。 N型源极 - 漏极区8和P型源极 - 漏极区12成形，并且形成层间绝缘膜16和多晶硅膜17。接触孔22-26成形，并且以低浓度的量将N型杂质离子注入整个表面，从而形成具有深结的杂质层9。 Al布线被成形，从而形成CMOS型半导体器件。

17. 发明专利

JP2556672B2 失效
公开(公告)号：JP2556672B2
公开(公告)日：1996-11-20
申请号：JP29416794
申请日：1994-11-29
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI
IPC分类号： H01L27/11 , H01L21/8244

18. 发明专利

JPH07211804A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07211804A
公开(公告)日：1995-08-11
申请号：JP29416994
申请日：1994-11-29
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KIYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To increase the level of integration of an SRAM by forming an insulating film above the gate electrode of an MISFET for driving, and forming a second conductivity type polycrystalline silicon film which is electrically connected with the drain region of the MISFET for driving and used as the gate electrode of an MISFET for load, above the insulating film. CONSTITUTION:An gate insulating film 5 is formed on the main surface of a P-type well region. An N type semiconductor region 11 which is used as an N type semiconductor region 8, a source region and a drain region is formed on the main surface part of a well region with which a gate electrode 7 is connected through an N-type semiconductor region 9 used as a part of a source region and a part of a drain region and a connection hole 6. A layer insulating film 12 is formed on the whole part of the substrate containing the upper part of the gate electrode 7, and a gate insulating film 15 is formed on the whole surface of the substrate, so as to cover a gate electrode 14. The channel forming regions 17A, the drain regions 17B, and the source regions 17C of MISFET's Qp1, Qp2 for loads are formed in order above the gate insulating film 15.

19. 发明专利

JPH03116866A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03116866A
公开(公告)日：1991-05-17
申请号：JP25190389
申请日：1989-09-29
申请人： HITACHI LTD
发明人： TAKAHASHI MASATO , MOTOYOSHI MAKOTO , SUZUKI NORIO , MEGURO SATOSHI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To prevent the retention of data by a method wherein an intrinsic region is formed of an N-type region of low concentration. CONSTITUTION:After a MISFET Q is formed, an interlaminar insulating film 2 of SiO2 is formed through a CVD method. Polycrystalline silicon is deposited on the whole face, which is patterned into a high resistor of prescribed pattern. Then, N-type impurity is ion-implanted to form an N-type region 3 of low concentration. In succession, P-type impurity is introduced into the N-type region 3 using a mask 4 of prescribed shape to form a P-type region 5 of low concentration. Then, the mask 4 is removed, and N-type impurity is introduced into N-type regions 3b and 3a of low concentration using a new mask 6 to form N-type regions 7 and 8 of high concentration respectively. In succession, the mask 6 is removed, an interlaminar insulating film 9 is formed through a CVD method, then a wiring layer 10 is formed, and the high concentration N-type regions 7 and 8 are connected to a feed power source Vcc and a memory node V1 respectively.

20. 发明专利

JPH01243544A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01243544A
公开(公告)日：1989-09-28
申请号：JP6953788
申请日：1988-03-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIMOTO TOSHIAKI , KOMORI KAZUHIRO , SUZUKI NORIO , MOTOYOSHI MAKOTO , HAGA SATORU
IPC分类号： H01L21/3205 , H01L21/60
摘要： PURPOSE:To effectively prevent halation by a method wherein an Al-based metal film and a conductive film composed of a conductive material whose high reflection factor is lower than that of Al are laminated one after another in a circuit formation region of a wafer and they are patterned. CONSTITUTION:An aluminum-based metal film 3 and a conductive film 4 composed of a conductive material whose light reflection factor is lower than that of the metal film 3 are laminated one after another in a circuit formation region of a semiconductor wafer 1. The metal film 3 and the conductive film 4 are patterned; a wiring part 5 is formed. A passivating film 8 is applied to the wiring part 5; a photoresist 9 is applied to the surface of the passivating film 8; holes 10 are made in prescribed parts. The metal film 3 is applied to the surface of the wafer 1; the resist 9 and the metal film 3 are removed by a lift-off method. By this setup, it is possible to effectively prevent halation when a mask pattern for wiring use is to be formed.

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