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11. 发明专利

JPS574152A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS574152A
公开(公告)日：1982-01-09
申请号：JP7818880
申请日：1980-06-10
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , YAMAUCHI TAKAHIKO
IPC分类号： G11C11/41 , G11C5/02 , G11C5/14 , G11C11/401 , H01L21/822 , H01L23/528 , H01L27/02 , H01L27/04 , H01L27/10
摘要： PURPOSE:To improve a signal transmittance speed between a buffer circuit and a decoder circuit by a method wherein both a signal line and a power supply line arranged around an inner circuit are wired only at the outside part of the wiring connecting the inner circuit with the buffer circuit. CONSTITUTION:Memory cell 2 and decoder circuit 3 are arranged at a central area of the semiconductor memory device 1'. Grounding wire 7' is arranged in an area surrounding these component elements. Several kinds of buffer circuits 41 to 46 are arranged below the grounding wire 7' or adjacent to the grounding wire 7'. A terminal of each of the circuits 41 to 46 which is applied for a connection between the decoder 3 and the cell 2 is arranged at an inner area of loop formed by the grounding wire 7', power supply line 6' is arranged at the outermost circumferential area of device 1', and a group of signal lines 5' among the circuits 41 to 46 is arranged inside of it. Thus, no bridge is found at the signal line to which a high speed signal transmittance is preferred, that is, the terminal or signal line arranged inwardly of the grounding wire 7' for the circuits 41 to 46, so a high speed signal transmittance may be performed.

12. 发明专利

JPS56110363A MULTIPLEXING CIRCUIT USING PLL 失效
公开(公告)号：JPS56110363A
公开(公告)日：1981-09-01
申请号：JP1311580
申请日：1980-02-06
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , MORITA TOSHIYUKI , ITOU HIDEAKI , SHIMOYAMA TSUNAYOSHI , TAKANO TOSHIHARU
IPC分类号： H04J3/06 , H03L7/06 , H03L7/08 , H04L7/033
摘要： PURPOSE:To make a mutual position relation between the data and the clock constant and thus ensure a steady operation of a multiplexing circuit, by providing a multiplying circuit and divider circuit and then feeding-back the output of the divider circuit to a phase comparator to control a voltage control type quartz oscillator. CONSTITUTION:The output of the m/n divider circuit 13 is fed back to the phase comparator PD, and the voltage control type quartz oscillator VCXO is controlled by the output of the comparator PD. At the same time, a waveform reproduction is given to the n-series signal by the output of the m/n multiplier circuit 11. Thus the phase relation is secured always constant based on the operation of a PLL among the 2-series signals CH1' and CH2' serving as the input of a parallel-serial conversion circuit and the 2-divided clock signal f0'CL, the 1-series signal CH' serving as the output of the parallel-serial conversion circuit and the output clock 2f0CL, even if a phase uncertain area such as a double multiplying circuit or the like exists within the loop of the PLL.

13. 发明专利

JPS5522238A DECODER CIRCUIT 失效
公开(公告)号：JPS5522238A
公开(公告)日：1980-02-16
申请号：JP9350278
申请日：1978-07-31
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , AZUMA KENJI , NOGUCHI EIJI
IPC分类号： G11C11/41 , G11C11/413 , G11C11/418 , G11C11/419 , H03M7/00
摘要： PURPOSE:To omit the gate for the clock and its wiring by including the clock information into one of the address signals, thus simplifying the constitution of the decoder circuit as well as reducing the occupied area. CONSTITUTION:Address signal A4* containing the clock information is produced from address signal 4A through the circuit comprising MOSFETQ11-Q16. Single conduction channel type MOSFETQ1 to which signal A4* is applied and FETQ1 to which signal A4* plus other address signal are applied are connected in series to opposite conduction channel type MOSFETQ2-Q6. The outpur is then drawn out at the joints of the above FET's via output line l in order to decrease one gate for the clock. The circuit to produce the address signal containing the clock information is required, but the constitution can be simplified greatly as a whole since the number of the gate is multiplied as much as the number of the column.

14. 发明专利

JPS60139015A PULSE GENERATING CIRCUIT 失效
公开(公告)号：JPS60139015A
公开(公告)日：1985-07-23
申请号：JP24453383
申请日：1983-12-27
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , KOSHIZUKA ATSUO , KOYOU KAZUTO
IPC分类号： H03K3/353 , G11C8/18 , H03K3/017 , H03K3/037 , H03K3/356 , H03K5/153 , H03K5/1532
摘要： PURPOSE:To produce pulses assuredly regardless of the timing of two signals which are complementary to each other by combining properly three logical gates. CONSTITUTION:The 1st input signal SA and the output of the 2nd NAND circuit 2 are applied to the 1st NAND circuit 1. An input signal complementary to the signal SA and the output of the circuit 1 are applied to the circuit 2. The outputs of both circuits 1 and 2 are applied to the 3rd NAND circuit 3. Then a pulse signal PA is delivered from the circuit 3. Thus it is possible to produce pulses assuredly regardless of the timing of two signals complementary to each other.

15. 发明专利

JPS58221537A Fixing system of frame synchronism 失效
标题翻译：框架同步固定系统
公开(公告)号：JPS58221537A
公开(公告)日：1983-12-23
申请号：JP10454382
申请日：1982-06-17
申请人： Fujitsu Ltd
发明人： ITOU HIDEAKI
IPC分类号： H04L7/08 , H04J3/06
CPC分类号： H04J3/0605
摘要： PURPOSE:To ensure synchronism in a short time, by securing the frame synchronism after putting frame synchronizing pattern into plural signals with multi- phase modulation to transmit them then performing comparison of patterns for all sequences at the receiving side to ensure the frame synchronism. CONSTITUTION:Data 1 and 2 are applied with FM31 at the transmitting side, and frame signals S1 and S2 supplied from a frame synchronizing signal generator 32 are applied to synthesizers 33 and 34 and transmitted as signals of sequences 1 and 2 respectively. While the signal of the sequence 1 is applied to a comparator 35 and a frequency converter 39, and the signal of the sequence 2 is applied to a comparator 36 and the converter 39 respectively at the receiving side. These comparators 35 and 36 compare the signals of sequences 1 and 2 with signals S1 and S2 supplied from a frame synchronizing signal generator 38 and the generator 38 of the sequence 2 respectively. The generator 38 is advanced when the patterns are coincident with each other between both signals. The same comparison is peformed again at the frame synchronizing signal adding position. If the frame synchronism is established, the additional bits are removed. Then a frequency conversion is carried out, and original signal data 1 and 2 are transmitted.
摘要翻译：目的：为了在短时间内确保同步，通过将帧同步模式置于多相信号中进行多相位调制传输，确保帧同步，然后执行接收侧所有序列的模式比较，确保帧同步。构成：数据1和2在发送侧应用FM31，并且从帧同步信号发生器32提供的帧信号S1和S2被分别施加到合成器33和34并分别作为序列1和2的信号传输。虽然序列1的信号被施加到比较器35和频率转换器39，并且序列2的信号分别在接收侧被施加到比较器36和转换器39。这些比较器35和36分别比较序列1和2的信号与从帧同步信号发生器38和序列2的发生器38提供的信号S1和S2。当图案在两个信号之间彼此重合时，发生器38前进。在帧同步信号添加位置再次进行相同的比较。如果帧同步建立，则删除附加位。然后进行频率转换，并且发送原始信号数据1和2。

16. 发明专利

JPS5825736A MEASURING CIRCUIT FOR SIGNAL BREAK TIME 失效
公开(公告)号：JPS5825736A
公开(公告)日：1983-02-16
申请号：JP12505181
申请日：1981-08-08
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , MORITA TOSHIYUKI , HODOHARA KIYOAKI
IPC分类号： H04B1/74 , H04B17/00
摘要： PURPOSE:To measure accurately the signal break time for current/stand-by switching or the like, by counting pulses having a constant period to measure the signal break time. CONSTITUTION:The output signal of a reference signal generator 21 is applied to not only a signal transmitting device 22 but also a phase adjuster 23. Since the delay time of the phase adjuster 23 is adjusted so as to be equal to the signal delay time in the transmitting device 22, an output 1 of the signal transmitting device 22 and an output 2 of the phase adjuster 23 have the same phase if no signal break is generated, and an output 3 of an exclusive OR gate 24 becomes ''0''. If a signal break is generated in the transmitting device 22, a ''1'' and ''0'' repeat signal corresponding to the time of the signal break appears in the output of the exclusive OR gate 24. Thus, the pulse output of an oscillator 27 is generated in an output signal 7 of an AND gate 28 during the signal break time, and a counter 29 counts the number of pulses to measure the signal break time.

17. 发明专利

JPS57150188A ASYNCHRONOUS TYPE STATIC MEMORY 失效
公开(公告)号：JPS57150188A
公开(公告)日：1982-09-16
申请号：JP3579181
申请日：1981-03-12
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , SUZUKI ATSUSHI
IPC分类号： G11C11/417 , G11C11/419
摘要： PURPOSE:To achieve equi-potential for data bus of an asynchronous static memory in a high speed in a small current consumption, by providing a short circuit with a pair of data bus lines and connecting the bus lines to a low potential power supply for a short time. CONSTITUTION:A pair of bit lines DB and anti-DB' of an asynchronous static memory are provided with a short circuit ST consisting of P type transistors (TRs) P1-P3 connecting both the lines and gate N type TRs N5 and N6 connecting the bit lines to a low potential power supply VSS. The TRs P1-P3 are controlled with a chip selection clock CS1 and the TRS N5 and N6 are controlled with a clock CS2 delayed for a prescribed amount from the clock CS1. Thus, they are connected to the power supply VSS only at a part of period of the standby period and the lines are of equal potential in high speed with a small power consumption. Then, the access at chip selection is made high in speed.

18. 发明专利

JPS56149813A ELASTIC SURFACE WAVE DEVICE 失效
公开(公告)号：JPS56149813A
公开(公告)日：1981-11-19
申请号：JP5282380
申请日：1980-04-23
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , WAKATSUKI NOBORU , MORITA TOSHIYUKI , ITOU HIDEAKI , HODOHARA KIYOAKI
IPC分类号： H03H9/25 , H03H3/08 , H03H9/02 , H03H9/05
摘要： PURPOSE:To prevent electric discharge of the element and caused by a pyroelectric effect, by coating the surface and the side of an elastic surface wave element which is used for the filter of VHF and UHF bands, etc., with an insulator. CONSTITUTION:The surface (the surface of the grid electrode 18 is also included) and the side of the elastic surface wave element 17 mounted on the bottom plate 16a of the metallic case 16 are coated with an insulating material 19. This insulating material 19 consists of an inorganic material such as SiO2, or an organic material such as polyamide resin, and SiO2, etc. are formed to several mum in thickness by means of vacuum deposition or sputtering. According to said constitution, the electric charge which has charged the surface of the element 17 due to a pyroelectric effect is shut off from air by the insulating material 19, electric discharge to the bottom plate 16a is prevented, also electric discharge to the grid electrode 18 is prevented, and generation of a noise caused by a pyroelectric effect is prevented.

19. 发明专利

JPS56117421A RETRIGGERABLE MULTIVIBRATOR 失效
公开(公告)号：JPS56117421A
公开(公告)日：1981-09-14
申请号：JP2020380
申请日：1980-02-20
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , MORITA TOSHIYUKI , ITOU HIDEAKI , HODOHARA KIYOAKI
IPC分类号： H03K3/02 , H03K3/033
摘要： PURPOSE:To eliminate the limitation of the working frequency, by constituting a retriggerable multivibrator with two flip-flops. CONSTITUTION:The time constants C1R1 and C2R2 of the two integral networks 7 and 8 are selected as C1R1>>C2R2. When a pulse signal having the period T0 shorter enough than the time constant C1R1 is applied to the clock terminal of each flip- flop, the flip-flop 1 is not set with its Q output signal 4 kept at a low level. On the other hand, if the period T0 of the input signal is larger enough than the constant C1R1, the time working state decided by 0.7C1R1 is kept to give a restoration. When the input signal pulses are supplied consecutively, the working time is started at the time point when the final pulse of the input signals that continue in the time interval less than 0.7C1R1.

20. 发明专利

JPS56117389A STATIC TYPE RANDOM ACCESS MEMORY 失效
公开(公告)号：JPS56117389A
公开(公告)日：1981-09-14
申请号：JP1801980
申请日：1980-02-16
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , SHIMADA HIROSHI
IPC分类号： G11C11/41 , G11C7/10 , G11C11/417 , G11C11/419
摘要： PURPOSE:To reduce the access time of readout for other cells immediately after the cell write-in in common use of the bit line, by connecting a short-circuit transistors showing ON resistance between a pair of bit lines and a pair of data bus lines. CONSTITUTION:RAM is constituted with a number of memory cells MC... between a pair of bit lines BL, BLB lines and short-circuit transistors T3, T4 showing ON- resistance are connected between a pair of data bus lines BS and BSB. The transistors T3, T4 are ON at readout/write-in, and a current flows via the transistor T3 until the potential difference between the lines BL and BLB after the information is written in the cell MC1. This is the same for the transistor T4, that is, the time when the potential between BL, BLB and the potential of the outputs SD, SDB of the sense amplifier SA are in agreement, is made faster than the case without the transistors T3, T4, and the readout access time for other common cells of the bit line pairs immediately after the write-in can be decreased.

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