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1. 发明专利

JPH01238000A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01238000A
公开(公告)日：1989-09-22
申请号：JP6610288
申请日：1988-03-18
申请人： FUJITSU LTD
发明人： YAMAUCHI TAKAHIKO
IPC分类号： G11C29/00 , G11C11/401 , G11C29/50
摘要： PURPOSE:To increase and decrease the potential of a bit line without changing a power source voltage and to realize many test conditions by impressing a voltage to one side out of respective pads corresponding to a signal line to supply a signal at the time of the primary test of a semiconductor memory device. CONSTITUTION:A memory cell 1 is provided at the intersection of bit lines BL and the inverse of BL connected through pull-up transistors TrQ1 and Q2 to a power source line 2 to supply a power source voltage VCC of a semiconductor memory device and derived through data transfers TrQ5 and Q6 to a sense amplifier S and a word line WL to intersect with the lines BL and the inverse of BL. Pull-up TrQ3 and Q4 different from the TrQ1 and Q2 are provided between the line 2 and the lines BL and the inverse of BL and pull-down TrQ7 and Q8 are provided between the lines BL and the inverse of BL and a ground. TrQ3, Q4 and Q7, Q8 are respectively made into the conducting condition with a signal from a signal line, the signal is derived to respective corresponding pads P1 and P2 and without changing the voltage VCC at the time of the primary test, the potential of the line BL and the inverse of BL is increased and decreased and with a simple constitution, a primary test is executed.

2. 发明专利

JPS6237468B2 失效
公开(公告)号：JPS6237468B2
公开(公告)日：1987-08-12
申请号：JP5115282
申请日：1982-03-31
申请人： FUJITSU LTD
发明人： AOYAMA KEIZO , YAMAUCHI TAKAHIKO , SEKI TERUO
IPC分类号： G11C11/412 , G11C11/41 , G11C11/413 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11

3. 发明专利

JPS60180159A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS60180159A
公开(公告)日：1985-09-13
申请号：JP3513084
申请日：1984-02-28
申请人： FUJITSU LTD
发明人： YAMAUCHI TAKAHIKO , AOYAMA KEIZOU
IPC分类号： G11C11/41 , H01L21/3205 , H01L21/82 , H01L21/8244 , H01L23/52 , H01L27/10 , H01L27/11
摘要： PURPOSE:To prevent short circuits among signal lines and power supply lines by pulling up the potential of bit lines to potential higher than that of the power supply lines and arranging the bit lines and the power supply lines so that spaces among the bit lines to each bit line pair and the power supply lines are made wider than spaces among adjacent bit line pairs. CONSTITUTION:The potential of bit lines is pulled up to potential higher than that of power supply lines, and spaces among the bit lines in each bit line pair and the power supply lines are made wider than spaces among adjacent bit line pairs. The bit line such as a bit line -BL0 is separated from the power supply line Vss, and brought close to another bit line BL1 by a section corresponding to the separating section. Consequently, a defective short circuit between the bit line -BL0 and the bit line BL1 is easy to be generated, but a critical short circuit between the bit line -BL0 and the power supply line Vss can be prevented. As a result, the bit lines and the power supply lines are separated by asymmetrically arranging the bit lines to contact regions CONTs, and critical short circuits can be obviated. Accordingly, the relief probability of defects by a redundancy circuit can be enhanced.

4. 发明专利

JPS609370B2 失效
公开(公告)号：JPS609370B2
公开(公告)日：1985-03-09
申请号：JP18307680
申请日：1980-12-24
申请人： FUJITSU LTD
发明人： AOYAMA KEIZO , YAMAUCHI TAKAHIKO
IPC分类号： H03K19/0948 , H03K5/02 , H03K17/06 , H03K17/687 , H03K19/017 , H03K19/094

5. 发明专利

JPS5958688A Decoder circuit 失效
标题翻译：解码器电路
公开(公告)号：JPS5958688A
公开(公告)日：1984-04-04
申请号：JP16827382
申请日：1982-09-29
申请人： Fujitsu Ltd
发明人： SEKI TERUO , YAMAUCHI TAKAHIKO , AOYAMA KEIZOU
IPC分类号： G11C11/413 , G11C8/10
CPC分类号： G11C8/10
摘要： PURPOSE: To attain circuit integration with small size and high speed, by providing a gate transistor(TR) inverting instanly a level of a node when a decode input is transited to a selecting state and a latch TR holding the level as it is until the input is changed.
CONSTITUTION: The node Q is at H level at non-selection, a TRN
82 is turned on, and a decode output X
4 is at L level. This L level is fed back to TRs P
81 , N
81 to turn on the TRP
81 for latching it. That is, a latch TRLT holds stably the output X
4 . When the mode is shifted to the selecting state, the decode input starts going to H level. A gate gulse ϕ is brought into H level for a short time. This pulse ϕ is applied to a gate TRN
70 , which is turned on. Thus, the level of the node Q is inverted instantly. The TRP
82 is turned on and the decoded output X
4 of H level is transmitted. This output is held stably, because the TRN
81 is turned on and a latch 4 is latched.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了实现小尺寸和高速度的电路集成，通过提供栅极晶体管（TR），当解码输入转换到选择状态时，提供一个节点的级别，以及保持级别的锁存器TR直到输入更改。构成：节点Q在非选择时处于H电平，TRN82导通，解码输出X4为L电平。该L电平反馈到TRs P81，N81以打开TRP81以将其锁存。也就是说，锁存器TRLT稳定地保持输出X4。当模式转移到选择状态时，解码输入开始变为H电平。一个门脉冲phi被带入H级短时间。该脉冲phi被施加到导通的门TRN70。因此，节点Q的电平立即反转。 TRP82导通，H电平的解码输出X4被发送。该输出保持稳定，因为TRN81被接通并且锁存器4被锁存。

6. 发明专利

JPS5840344B2 失效
公开(公告)号：JPS5840344B2
公开(公告)日：1983-09-05
申请号：JP7818880
申请日：1980-06-10
申请人： FUJITSU LTD
发明人： ITO HIDEAKI , YAMAUCHI TAKAHIKO
IPC分类号： G11C11/41 , G11C5/02 , G11C5/14 , G11C11/401 , H01L21/822 , H01L23/528 , H01L27/02 , H01L27/04 , H01L27/10

7. 发明专利

JPS6053400B2 失效
公开(公告)号：JPS6053400B2
公开(公告)日：1985-11-25
申请号：JP19526281
申请日：1981-12-04
申请人： FUJITSU LTD
发明人： SEKI TERUO , YAMAUCHI TAKAHIKO , AOYAMA KEIZO
IPC分类号： G11C11/41 , G11C7/22 , G11C11/413 , G11C11/417

8. 发明专利

JPS5957525A Cmis circuit device 失效
标题翻译： CMIS电路设备
公开(公告)号：JPS5957525A
公开(公告)日：1984-04-03
申请号：JP16751182
申请日：1982-09-28
申请人： Fujitsu Ltd
发明人： AOYAMA KEIZOU , YAMAUCHI TAKAHIKO , SEKI TERUO
IPC分类号： H03K19/0948 , G11C8/18 , H03K19/00 , H03K19/096 , H03K19/094
CPC分类号： H03K19/0016 , G11C8/18 , H03K19/0963
摘要： PURPOSE: To realize a battery backup mode even with any of two chip selecting signals in opposite phase with each other, by combining three CMIS inverters.
CONSTITUTION: An inverter IV1 is formed by connecting MISFETs Q19∼21 in series between a power supply and ground. One inverting chip selecting signal is applied to a gate of the FETQ19 and the other chip selecting signal is applied to gates of the FETs Q20, Q21 respectively. An inverted chip selecting signal is applied to an output of the inverter IV1 and an internal chip selecting signal formed with the inverter IV2 is inverted at the inverter IV3 and applied to an input circuit IPC. Thus, the battery backup mode is realized with any of the two chip selecting signal opposite in phase with each other.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过组合三个CMIS逆变器，即使使用两个相互相反的芯片选择信号，即可实现电池备份模式。构成：通过将MISFET Q19-21串联连接在电源和地之间来形成反相器IV1。一个反相芯片选择信号被施加到FETQ19的栅极，另一个芯片选择信号分别施加到FET Q20，Q21的栅极。反相芯片选择信号被施加到反相器IV1的输出，并且由反相器IV2形成的内部芯片选择信号在反相器IV3处反相并施加到输入电路IPC。因此，利用彼此相位相反的两个芯片选择信号中的任何一个来实现电池备份模式。

9. 发明专利

JPS5919354A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5919354A
公开(公告)日：1984-01-31
申请号：JP12917782
申请日：1982-07-24
申请人： Fujitsu Ltd
发明人： YAMAUCHI TAKAHIKO , SEKI TERUO , AOYAMA KEIZOU
IPC分类号： H01L23/522 , H01L21/768 , H01L23/485 , H01L21/88
CPC分类号： H01L23/485 , H01L21/76895 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： PURPOSE:To reduce the occupying area of a contacting region in a structure that two adjacent conductive layers are connected by the third conductive layer by narrowing the end of one conductive layer. CONSTITUTION:A field oxidized film 12, the first polycrystalline silicon layer 15, a source and drain N type region 14, a nitrided silicon film 16 and the second silicon layer 17 are formed on a P type silicon substrate 11, and the first layer 15 and the region 14 are connected by the layer 17. The pattern of the layer 15 is narrowed at the end to be disposed in a contacting window 16', and dimensions L1, L2 necessary to secure the contact to the layers are secured by considering the displacement margin. Since the end of the layer 15 is narrowed in width, the dimensions L1, L2 have superposition, and the area of the contact can be reduced.
摘要翻译：目的：通过使一个导电层的端部变窄，在两个相邻的导电层通过第三导电层连接的结构中减小接触区域的占据面积。构成：在P型硅衬底11上形成场氧化膜12，第一多晶硅层15，源极和漏极N型区14，氮化硅膜16和第二硅层17，第一层15 并且区域14由层17连接。层15的图案在末端变窄以设置在接触窗口16'中，并且通过考虑到位移边际。由于层15的端部的宽度变窄，尺寸L1，L2具有叠加，并且可以减小接触面积。

10. 发明专利

JPS58101525A LOGICAL CIRCUIT 失效
公开(公告)号：JPS58101525A
公开(公告)日：1983-06-16
申请号：JP20107781
申请日：1981-12-14
申请人： FUJITSU LTD
发明人： SEKI TERUO , YAMAUCHI TAKAHIKO , AOYAMA KEIZOU
IPC分类号： H03K19/0948 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/418 , H03K19/017 , H03K19/0944
摘要： PURPOSE:To eliminate the difference of response times due to input conditions, by connecting MOS TRs for the number of input terminals' share in series and driving a plurality of the said series circuits connected in parallel with an input signal. CONSTITUTION:In case of 2-input NAND gate, two sets of series connections of two MOS TRs are connected in parallel with gates T1, T2. When an input terminal IN1 is ''H'' level and an input terminal IN2 is ''L'' level, since TRs T2 and T31 turn on and TRs T1, T41 turn off, the potential of a connecting point NB of the TRs T31, T41 is an ''H'' level and the potential at a connecting point NC is an ''L'' level. In switching IN2 from ''L'' to ''H'' level, TRT2 is set off and TRT42 is set on, and an output OUT goes from ''H'' to ''L'' quickly with the effect of the node NC at low potential side.

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