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1. 发明专利

JPH01181237A NONBREAK CHANGEOVER METHOD 失效
公开(公告)号：JPH01181237A
公开(公告)日：1989-07-19
申请号：JP509688
申请日：1988-01-13
申请人： FUJITSU LTD
发明人： OIDE KENICHI , HODOHARA KIYOAKI
IPC分类号： H04B1/74
摘要： PURPOSE:To preclude the possibility of a signal sent from an active line from being affected from a signal sent from a standby line by inserting the 2nd switch between a distribution panel and the 1st switch of an active line and turning off the 2nd switch when no changeover is implemented. CONSTITUTION:When the active line is not faulty, since part of a test signal extracted by an R-LOG15 through a standby line is sent to a test signal detector PD via a U/B converter 16 and a reception changeover switch R-SW1 and the remaining part is distributed by the distribution panel 2 and fed to a switch SW41. Since the moving part of the said switch is connected to ground, the possibility of the test signal affecting the unipolar signal is considerably precluded. If the active line is faulty, a sending end parallel switch T-SW1 is driven by a sending end parallel instruction from the reception end, a signal through the active line is fed also to the standby line to cause the parallel transmission state.

2. 发明专利

JPS6420729A CODING CIRCUIT 失效
公开(公告)号：JPS6420729A
公开(公告)日：1989-01-24
申请号：JP17750387
申请日：1987-07-16
申请人： FUJITSU LTD
发明人： HODOHARA KIYOAKI
IPC分类号： H03M13/00
摘要： PURPOSE:To attain high speed operation by clearing a storage means after a residual bit is obtained before the information bit to be inputted next is divided. CONSTITUTION:A storage means 5 connected to the input side of the storage means of the final stage in an arithmetic means 4 and not receiving a clear pulse is provided and an output of the arithmetic means is sent to a changeover means 6 via the storage means 5. That is, when the final bit of the residual bit is fetched in the storage means at the final stage and the storage means 5 in the arithmetic means 4, since a clear pulse is fed to the arithmetic means 4, the final bit of the residual bit fetched in the storage means of the final stage is cleared and the final bit fetched in the storage means 5 is outputted as it is to the changeover means 6. Thus, since the clear pulse and the outputted residual bit have one bit width, the storage means have only to have the same performance and the possibility of disabling high speed operation is precluded.

3. 发明专利

JPS631121A ERROR CORRECTION SYSTEM 失效
公开(公告)号：JPS631121A
公开(公告)日：1988-01-06
申请号：JP14282386
申请日：1986-06-20
申请人： FUJITSU LTD
发明人： HODOHARA KIYOAKI
IPC分类号： H03M13/00
摘要： PURPOSE:To perform generation of a check bit and error correction with a low-speed operation function by performing the division processing to obtain the check bit for each sequence in the transmission side and calculating a syndrome for each sequence to perform error correction in the reception side. CONSTITUTION:In the transmission side, dividing circuits 1-1-1-n which divide nk-number of information bits in accordance with a generating function correspondingly to n-number of sequences CH1-CHn, and the remainder of each division result is defined as nm-number of check bits, and nm-number of check bits of each of successively selected sequences are added to k-number of bits of the sequence, and they are multiplexed by a multiplexing part 3 and are transmitted. In the reception side, syndrome calculating circuits 2-1-2-n are provided correspondingly to n-number of sequences, and syndrome calculation is performed with nk-number of information bits and nm-number of check bits of the corresponding sequence with respect to information bits and check bits of respective sequences CH1-CHn demultiplexed by a demultiplexing part 4, and bit error correction for each sequence is performed in a bit correcting part 5.

4. 发明专利

JPS62247655A PHASE UNCERTAINTY ELIMINATING METHOD 失效
公开(公告)号：JPS62247655A
公开(公告)日：1987-10-28
申请号：JP8284586
申请日：1986-04-10
申请人： FUJITSU LTD
发明人： HODOHARA KIYOAKI
IPC分类号： H04L27/34 , H04L27/00
摘要： PURPOSE:To eliminate the phase uncertainty of a received signal by inserting the frame bits that are not affected by the phase uncertainty to the 2nd and following paths together with a phase difference detection bit put into the 1st path.. CONSTITUTION:The phase difference detection bit and the frame bit are put into the signals of the 1st and 2nd paths for each fixed cycle out of those outputs of an error correcting code part 201 through a phase difference detection bit inserting part 202 and a frame bit inserting part 203 respectively. These signal undergo the gray/natural conversion via a gray/natural converting part 204 and then modulation via a modulating part 205 and are transmitted via a transmitting part 206.

5. 发明专利

JPS60200631A CODE ERROR DETECTING CIRCUIT 失效
公开(公告)号：JPS60200631A
公开(公告)日：1985-10-11
申请号：JP5767984
申请日：1984-03-26
申请人： FUJITSU LTD
发明人： HODOHARA KIYOAKI
IPC分类号： H04J3/07 , H04J3/06
摘要： PURPOSE:To detect an error even if a jitter of the maximum (m)-bit exists between sequences by providing an (m)-bit elastic memory on other sequence, extending 1 bit to an (m)-bit portion, and detecting an error by a comparing circuit based on this (m)-bit portion and 1 bit of one sequence as a reference. CONSTITUTION:In the transmitting side, a test signal sent out of a test signal generator 8 driven by a clock from a clock generator 7 is converted to a test signal of two sequences having a delay difference of (n) bits and sent out as a test signal of a sequence 1 and a sequence 2 together with a clock. In the receiving side, the test signal of the sequence 1 which has passed through a delaying circuit 21 is written on an (m)-bit elastic memory 23 by the clock of the sequence 1 which has passed through a write counter 22 of an (m)-bit period. The test signal of the sequence 1 written in the (m)-bit elastic memory 23 is read out successively by an (m)-bit selector circuit 24 driven by a clock of the sequence 2 which has passed through a read-out counter 25 of an (m)-bit period and compared with the test signal of the sequence 2 by a comparing circuit 16, and the write counter 22 is controlled by a control means 35 so that an output pulse of the comparing circuit 16 is decreased.

6. 发明专利

JPS60151981A COAXIAL CABLE CONNECTING SYSTEM 失效
公开(公告)号：JPS60151981A
公开(公告)日：1985-08-10
申请号：JP869084
申请日：1984-01-20
申请人： FUJITSU LTD
发明人： HODOHARA KIYOAKI , KOBAYAKAWA KAZUE
IPC分类号： H01R9/05

7. 发明专利

JPS56146316A ELASTIC SURFACE WAVE DEVICE 失效
公开(公告)号：JPS56146316A
公开(公告)日：1981-11-13
申请号：JP4857380
申请日：1980-04-15
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , ITOU HIDEAKI , MORITA TOSHIYUKI , HODOHARA KIYOAKI
IPC分类号： H03H9/25 , H03H3/08 , H03H9/02 , H03H9/05
摘要： PURPOSE:To prevent not only the concentration of electric charge caused by the pyroelectric effect but the discharge on the end face of an elastic surface wave element, by rounding the corner part where the surface and the side face of said wave element adjoin with each other and the corner part where the side faces adjoin with each other. CONSTITUTION:The elastic surface wave element 17 is adhered to the bottom plate 16a via the adhesive 21 when the element 17 is stored into the metallic case 16. Then the corner part where the surface and the side face of the element 17 adjoin with each other is rounded 22, and at the same time the corner part where the side faces adjoin with each other is also rounded 23. For such elastic surface element, the electric charge caused on the element surface by the pyroelectric effect is prevented from concentrating in the corner part. At the same time, the discharge given to the plate 16a of the case 16 from the element surface can be avoided.

8. 发明专利

JPS56119547A DETECTING CIRCUIT FOR BREAKING OF SIGNAL AND MARK RATE 失效
公开(公告)号：JPS56119547A
公开(公告)日：1981-09-19
申请号：JP2185880
申请日：1980-02-23
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , MORITA TOSHIYUKI , ITOU HIDEAKI , HODOHARA KIYOAKI
IPC分类号： H04L1/00 , H04L1/20 , H04L25/02
摘要： PURPOSE:To independently determine the detection limit for breaking of signal through causing the limit of the detection mark rate to approach 0 and 1, by comparing the output of the integrating circuit, which has a time constant longer than that of the integrating circuit connected to retriggerable multivibrator, with the reference voltage. CONSTITUTION:When input signal 1 of pulse period t1 shorter than time constant CXRX of integrating circuit 14 is given to retriggerable multivibrator 11, Q' output signal 2 continues to be 0 and does not generate the alarm signal. When input signal 1 of pulse period t2 near time constant CXRX is given, output 2 repeates the operation of 0, 1 and averages them to generate the output signal, and pulse perior t2 becomes longer; and when it exceeds the threshold, alarm is generated. If instantaneous breaking sufficently longer than time constant R1C1 of integrating circuit 17 is generated in input signal 1, the alarm signal is generated when output signal 3 of integrating circuit 17 increases and exceeds the threshold voltage. If instantaneous break shorter than time constant R1C1 in the input signal, output signal 3 which does not reach the threshold voltage is reduced, and so alarm is not generated.

9. 发明专利

JPS5592042A PHASE LOCK LOOP CIRCUIT 失效
公开(公告)号：JPS5592042A
公开(公告)日：1980-07-12
申请号：JP16524178
申请日：1978-12-31
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , HODOHARA KIYOAKI , ITOU HIDEAKI
IPC分类号： H03L7/085 , H03K5/26 , H03L7/08
摘要： PURPOSE:To make it possible to operate a phase lock loop in a very high speed by combining and using FFs which are operated only by rise and break of clock pulses. CONSTITUTION:Input signal IN is subjected to 1/N frequency division and is sent to phase comparator PC, and the output of voltage control oscillator VCO is applied to comparator PC through frequency converter PCT and a 1/N frequency divider. The output of comparator PC is used for frequency control of oscillator VCO through an LPF. In this case, in comparator PC, FF3 is operated at rise and break points of a pulse to be divided by ''2'', and FF4 uses the output of FF4 to be operated at the rise or break point of the pulse, and outputs of FF3 and FF4 are given to exclusive OR circuit EXEOR. As a result, the phase lock loop can be operated in a very high speed.

10. 发明专利

JPH02277332A SCRAMBLE CIRCUIT 失效
公开(公告)号：JPH02277332A
公开(公告)日：1990-11-13
申请号：JP9811489
申请日：1989-04-18
申请人： FUJITSU LTD
发明人： HODOHARA KIYOAKI
IPC分类号： H04L27/18 , H04L7/00
摘要： PURPOSE:To prevent production of a code error by providing a differential arithmetic unit. CONSTITUTION:A differential arithmetic unit 2 applies a differential processing opposite to 4-adic sum logic to a random code output Pn of an M-series pattern generator 1 and outputs Pn-Pn-1 (mod 4) to an exclusive OR circuit 3. The exclusive OR circuit 3 applies the exclusive OR processing between the Pn-Pn-1 (mod 4) being an output of the differential arithmetic unit 2 and an input digital main signal Dn and outputs a processing output with low degree of randomness to an additive arithmetic unit 4, which applies the additive processing to the output of the exclusive OR circuit 3 and outputs a scramble signal with randomness equal to that of the M-series pattern generator 1 of an output D''n. Thus, a scramble signal with high random degree is obtained and the production of a code error is less.

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