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11. 发明专利

JP2008270716A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2008270716A
公开(公告)日：2008-11-06
申请号：JP2007330223
申请日：2007-12-21
申请人： Denso Corp , 株式会社デンソー
发明人： TAGUCHI SHINICHIRO , ISHIKAWA YASUYUKI , SUZUKI AKIRA , ISHIHARA HIDEAKI
IPC分类号： H01L21/822 , G05F1/56 , H01L27/04
CPC分类号： G05F1/56
摘要： PROBLEM TO BE SOLVED: To prevent excessive voltage and current when a short circuit occurs between adjacent terminals. SOLUTION: An IC 22 has power supply circuits 3, 4 selectively actuating in accordance with a selection signal SEL. The terminal of the IC 22 includes a low-potential power side terminal 8, a control-signal output terminal 9 to output a control signal REF from the power supply circuit 3 to a transistor 2, a voltage output terminal 11 to output a power voltage Vo from the power supply circuit 4 to a power supply output terminal 15, a phase-compensating input terminal 10 to input a phase-compensating signal AMPO from the transistor 2 to the push-pull output circuit 32 of the power supply circuit 3, and a high-potential side power supply terminals 6, 7. These terminals are arranged adjacently in the order described above. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了在相邻端子之间发生短路时防止过大的电压和电流。解决方案：IC22具有根据选择信号SEL选择性地启动的电源电路3,4。 IC22的端子包括低电位侧端子8，控制信号输出端子9，用于从电源电路3向晶体管2输出控制信号REF，电压输出端子11输出电源电压 Vo从电源电路4到电源输出端子15，相位补偿输入端子10将相位补偿信号AMPO从晶体管2输入到电源电路3的推挽输出电路32，以及高电位侧电源端子6,7，这些端子以上述顺序相邻配置。版权所有（C）2009，JPO＆INPIT

12. 发明专利

JP2008269066A Power circuit and power supply circuit system 审中-公开
标题翻译：电源电路和电源电路系统
公开(公告)号：JP2008269066A
公开(公告)日：2008-11-06
申请号：JP2007108254
申请日：2007-04-17
申请人： Denso Corp , 株式会社デンソー
发明人： SUZUKI AKIRA , ISHIKAWA YASUYUKI
IPC分类号： G05F1/56
摘要： PROBLEM TO BE SOLVED: To provide a power circuit and a power supply circuit system capable of preventing an output voltage from becoming out of control by the currents flowing into a power output line, while reducing increase in circuit scale.
SOLUTION: In a series regulator type power circuit 13, a diode 22 is connected between a power output terminal 10 and a base of a transistor 12 while using the power output terminal 10 side as an anode. When the output voltage VCL is increased beyond a target value by inflow of the current into the power output line 23 from the outside of the power circuit 13, an operational amplifier 3 reduces a base voltage of the transistor 12, and the diode 22 is biased forward. The current flowing into the power output line 23 flows to the ground via the diode 22 and the transistor in an output step of the operational amplifier 3.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种电力电路和电源电路系统，其能够防止输出电压由流入电力输出线的电流失控，同时减小电路规模的增加。解决方案：在串联调节器型电源电路13中，在将功率输出端子10侧用作阳极的同时，在功率输出端子10和晶体管12的基极之间连接二极管22。当通过从电源电路13的外部流入电力输出线23将输出电压VCL增加到目标值以上时，运算放大器3降低晶体管12的基极电压，并且二极管22被偏置前锋。在运算放大器3的输出步骤中，流入功率输出线路23的电流经由二极管22和晶体管流到地面。（C）2009，JPO＆INPIT

13. 发明专利

JP2008148246A Oscillation circuit 审中-公开
标题翻译：振荡电路
公开(公告)号：JP2008148246A
公开(公告)日：2008-06-26
申请号：JP2006336151
申请日：2006-12-13
申请人： Denso Corp , 株式会社デンソー
发明人： SUZUKI AKIRA , ISHIKAWA YASUYUKI
IPC分类号： H03K3/0231 , H03K5/08
摘要： PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of extracting a high-speed clock signal using an analog comparator. SOLUTION: An upper limit voltage and a lower limit voltage to be applied to a plus terminal of a comparator 4 are made variable, thereby setting the upper limit voltage and the lower limit voltage utilizing a switching box 1. Thus, a user operates switches S1-S2 of the switching box 1 to connect input terminal I1-I2 to output terminals T1-T6 in such a way that a first differential voltage that is a differential voltage between a power supply voltage VDD and the upper limit voltage, matches a second differential voltage that is a differential voltage between a ground voltage GND and the lower limit voltage. As a result, a frequency can be adjusted without changing a duty ratio of a clock signal extracted from the present oscillation circuit. As a result, a high-speed clock signal keeping the duty ratio can be extracted. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够使用模拟比较器提取高速时钟信号的振荡电路。解决方案：施加到比较器4的正端子的上限电压和下限电压是可变的，从而利用开关盒1设定上限电压和下限电压。因此，用户操作开关盒1的开关S1-S2，将输入端子I1-I2连接到输出端子T1-T6，使得作为电源电压VDD和上限电压之间的差分电压的第一差分电压匹配第二差分电压是地电压GND与下限电压之间的差分电压。结果，可以在不改变从本振荡电路提取的时钟信号的占空比的情况下调整频率。结果，可以提取保持占空比的高速时钟信号。版权所有（C）2008，JPO＆INPIT

14. 发明专利

JP2006166280A Interface circuit 有权
标题翻译：接口电路
公开(公告)号：JP2006166280A
公开(公告)日：2006-06-22
申请号：JP2004357581
申请日：2004-12-10
申请人： Denso Corp , 株式会社デンソー
发明人： TEJIMA YOSHINORI , ISHIKAWA YASUYUKI , MIZAWA MASATOYO , ISHIHARA HIDEAKI
IPC分类号： H03K19/0175 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To accomplish an interface circuit capable of reducing a layout area.
SOLUTION: A source of an NMOS transistor N1 is connected to an external input terminal VIN of -1V to 6V, a source of a PMOS transistor P1 is connected to its source, and an inverter is connected to its drain. When threshold voltages VTN1, VTP1 of N1 and P1 are set to 1V and gate voltages VGN1, VGP1 are set to 4V and 0V, respectively, the voltage to be given to a node A is limited within a range of -1V to 3V. Furthermore, the voltage to be given to a node B is limited within a range of 1V to 3V. Namely, the range of output voltages of N1 and P1 can be suppressed narrower than the range of voltages to be given to the external input terminal VIN.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：实现能够减少布局面积的接口电路。解决方案：NMOS晶体管N1的源极连接到-1V至6V的外部输入端VIN，PMOS晶体管P1的源极连接到其源极，反相器连接到其漏极。当N1和P1的阈值电压VTN1，VTP1被设置为1V并且栅极电压VGN1，VGP1分别被设置为4V和0V时，给予节点A的电压被限制在-1V至3V的范围内。此外，给予节点B的电压被限制在1V至3V的范围内。即，N1和P1的输出电压的范围可以被抑制得比外部输入端子VIN的电压范围窄。版权所有（C）2006，JPO＆NCIPI

15. 发明专利

JP2006164098A Power circuit 审中-公开
标题翻译：电源电路
公开(公告)号：JP2006164098A
公开(公告)日：2006-06-22
申请号：JP2004357580
申请日：2004-12-10
申请人： Denso Corp , 株式会社デンソー
发明人： TEJIMA YOSHINORI , ISHIKAWA YASUYUKI , MIZAWA MASATOYO , ISHIHARA HIDEAKI
IPC分类号： G05F1/56
摘要： PROBLEM TO BE SOLVED: To provide a power circuit that can reconcile the high-speed suppression of variations in supply voltage supplied to a microcomputer and low power consumption.
SOLUTION: When the operation mode of a microcomputer 1 is a normal operation mode, a detection signal MS output from a load current monitor 4 is in a high level to switch on an NMOS transistor 103 of a constant current part 100a of an operational amplifier 2, so that a constant current i1 is made to have a magnitude decided by a resistor 101 and increased to accelerate the response speed of the operational amplifier 2. When the operation mode of the microcomputer 1 is a low power consumption mode, the detection signal MS is in a low level to switch off the NMOS transistor 103, so that the constant current i1 is reduced, to suppress the power consumption of the operational amplifier 2.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够调节对提供给微型计算机的电源电压的变化的高速抑制和低功耗的电源电路。解决方案：当微型计算机1的操作模式是正常工作模式时，从负载电流监视器4输出的检测信号MS处于高电平，以接通一个恒定电流部分100a的NMOS晶体管103 运算放大器2，使得恒定电流i1具有由电阻器101确定的幅度，并且增加以加速运算放大器2的响应速度。当微计算机1的操作模式是低功耗模式时，检测信号MS处于低电平以关断NMOS晶体管103，从而减小恒定电流i1，以抑制运算放大器2的功耗。（C）2006年，JPO和NCIPI

16. 发明专利

JP2006101465A Clamping circuit device 有权
标题翻译：钳位电路设备
公开(公告)号：JP2006101465A
公开(公告)日：2006-04-13
申请号：JP2004314012
申请日：2004-10-28
申请人： Denso Corp , 株式会社デンソー
发明人： MIZAWA MASATOYO , ISHIKAWA YASUYUKI , SUZUKI AKIRA , TEJIMA YOSHINORI , ISHIHARA HIDEAKI , MURAMATSU TOSHIJI , NASU TADASHI
IPC分类号： H03G11/02
摘要： PROBLEM TO BE SOLVED: To provide a clamping circuit device which can be constituted of fewer elements' in a simple fashion. SOLUTION: Reference voltages V1, V2 are set up by a series circuit of an FET 1, a resistor 2 and an FET 3. Gate potentials V4, V5 of FETs 7, 11 are set up, by performing addition and subtraction of these reference voltages and a reference voltage V2 generated by a bandgap reference circuit 6, respectively using an addition circuit 4 and a subtraction circuit 9. The clamp circuit device 12 is configured by connecting together a source of the one FET 7 with its drain connected with the power supply and a source of the other FET 11 with its drain being connected with the ground to an input terminal of a control IC unit 8. Thus, voltage is clamped to [V4+Vtp], when an excessive voltage of positive polarity is applied to an input terminal, and the voltage is clamped to [V5-Vtn], when an excessive voltage of negative polarity is applied. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：以简单的方式提供可由较少元件构成的钳位电路装置。
解决方案：参考电压V1，V2由FET1，电阻器2和FET3的串联电路建立。FET7,11的栅极电位V4，V5通过执行加法和减法这些参考电压和由带隙参考电路6分别使用加法电路4和减法电路9产生的参考电压V2。钳位电路器件12通过将一个FET 7的源极与其漏极连接在一起而构成电源和另一个FET 11的源极，其漏极与接地连接到控制IC单元8的输入端。因此，当正极性过大的电压为（V4 + Vtp）时，电压被钳位为[V4 + Vtp] 施加到输入端子，并且当施加负极性的过大电压时，电压被钳位到[V5-Vtn]。版权所有（C）2006，JPO＆NCIPI

17. 发明专利

JP2014212475A 半導体集積回路装置审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2014212475A
公开(公告)日：2014-11-13
申请号：JP2013088311
申请日：2013-04-19
申请人：株式会社デンソー , Denso Corp
发明人： ISHIKAWA YASUYUKI
IPC分类号： H03F3/45
CPC分类号： H03F3/45
摘要：【課題】位相補償用容量およびノイズ除去用容量による差動増幅部の電圧変動を抑制する。【解決手段】半導体基板に一体に形成される半導体集積回路装置で、差動増幅部1、利得部2、利得・出力部3を有する。利得・出力部3の出力端子と入力端子との間に位相補償コンデンサ4を接続し、利得・出力部3の入力端子と回路のグランド端子との間にノイズ除去コンデンサ5を接続する。高周波ノイズに晒された場合に、接地端子などからノイズが進入して寄生インピーダンスで電圧変動が生じるのは利得部2の出力端子部分となり、差動増幅部1に変動を来すのを抑制できる。【選択図】図1
摘要翻译：要解决的问题：为了抑制差分放大部分中的电压波动，电压波动由相位补偿电容和噪声消除电容引起。解决方案：一种半导体集成电路器件，与半导体衬底一体形成并具有差分放大部分1，增益部分2和增益输出部分3包括：连接在增益输出部分3的输出端和输入端之间的用于相位补偿的电容器4; 以及连接在增益输出部3的输入端子与电路的接地端子之间的用于消除噪声的电容器5。当半导体电路器件受到高频噪声时，噪声从接地端子等进入，并且由于寄生阻抗引起的电压波动发生在增益部分2的输出端部分，从而抑制差动波动的发生放大部分1。

18. 发明专利

JP2008113406A Frequency-multiplied clock signal output circuit 审中-公开
标题翻译：频率补偿时钟信号输出电路
公开(公告)号：JP2008113406A
公开(公告)日：2008-05-15
申请号：JP2007123404
申请日：2007-05-08
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI , TEJIMA YOSHINORI , ISHIHARA HIDEAKI
IPC分类号： H03K5/00 , H03L7/099
CPC分类号： H03L7/0995 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To provide a frequency-multiplied clock signal output circuit which can output a frequency-multiplied clock signal in a stable state even when the frequency of a clock signal output from a ring oscillator becomes higher.
SOLUTION: In a DPLL circuit 1, when the size of a data value which is output from a data latch circuit 52 and should be naturally set in a 11-bit down-counter 54d becomes equal to or more than 12 bits, an overflow preventing circuit 3 substitutes the 11-bit data for the data value.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使当从环形振荡器输出的时钟信号的频率变高时，也可以提供能够在稳定状态下输出倍频时钟信号的倍频时钟信号输出电路。解决方案：在DPLL电路1中，当从数据锁存电路52输出并且应当自然地设置在11位递减计数器54d中的数据值的大小变为等于或大于12位时，溢出防止电路3将11位数据替换为数据值。版权所有（C）2008，JPO＆INPIT

19. 发明专利

JP2007243808A Reset detection circuit in semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路中的复位检测电路
公开(公告)号：JP2007243808A
公开(公告)日：2007-09-20
申请号：JP2006065958
申请日：2006-03-10
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI , SUZUKI AKIRA
IPC分类号： H03K17/22
CPC分类号： H03K5/19 , H03K5/24
摘要： PROBLEM TO BE SOLVED: To prevent a logic circuit or a RAM from not being reset since it can not be accurately detected whether a voltage VDD is equal with or higher than a reset voltage of the logic circuit and a RAM holding voltage V-RST.
SOLUTION: While detecting that a voltage 5VIN becomes lower than a minimum operating voltage V-MIN at all the time in power source start-up, battery cutoff, reduction of a voltage VDD caused by surge and power source falling, it is determined whether the voltage VDD is equal with or higher than the reset voltage and the RAM holding voltage V-RST. When the voltage 5VIN becomes lower than the minimum operating voltage V-MIN, reset detection of the logic circuit or the RAM is performed regardless of whether the voltage VDD is equal with or higher than the reset voltage and the RAM holding voltage V-RST.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了防止逻辑电路或RAM不被复位，因为不能精确地检测电压VDD是否等于或高于逻辑电路的复位电压和RAM保持电压V -RST。
解决方案：在电源启动，电池切断，电涌和电源下降引起的电压VDD降低时，检测到5VIN的电压始终低于最小工作电压V-MIN，确定电压VDD是否等于或高于复位电压和RAM保持电压V-RST。当电压5VIN变得低于最小工作电压V-MIN时，无论电压VDD是否等于或高于复位电压和RAM保持电压V-RST，都执行逻辑电路或RAM的复位检测。版权所有（C）2007，JPO＆INPIT

20. 发明专利

JP2006295320A Multiplied clock signal output circuit 审中-公开
标题翻译：多路时钟信号输出电路
公开(公告)号：JP2006295320A
公开(公告)日：2006-10-26
申请号：JP2005110075
申请日：2005-04-06
申请人： Denso Corp , 株式会社デンソー
发明人： ISHIKAWA YASUYUKI , TEJIMA YOSHINORI , ISHIHARA HIDEAKI
IPC分类号： H03K5/00 , G06F1/04 , H03K3/03
摘要： PROBLEM TO BE SOLVED: To provide a multiplied clock signal output circuit capable of stabilizing the frequency of a multiplied clock signal without the need for implementing measures of power supply isolation resulting in a cost increase. SOLUTION: The multiplied clock signal output circuit 1 is provided with a count value averaging circuit 3, which averages results of counts by a plurality of number of times by a counter for counting a period of a reference clock signal PREF within a control period, and a digital control oscillation circuit 2 applies arithmetic processing to averaged data DTAVE to produce the multiplied clock signal. COPYRIGHT: (C)2007,JPO&INPIT

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