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121. 发明专利

JP2012104513A Semiconductor device, semiconductor assembly member, and manufacturing method of the semiconductor device 审中-公开
标题翻译：半导体器件，半导体器件组件和半导体器件的制造方法
公开(公告)号：JP2012104513A
公开(公告)日：2012-05-31
申请号：JP2010248867
申请日：2010-11-05
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDA TETSURO , IMAMURA TOMOMI
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/329 , H01L21/768 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L23/522 , H01L27/04 , H01L27/088 , H01L29/47 , H01L29/861 , H01L29/868 , H01L29/872
CPC分类号： H01L25/072 , H01L22/14 , H01L23/3107 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/41741 , H01L29/42372 , H01L29/42376 , H01L29/7811 , H01L29/7813 , H01L2224/04034 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/06051 , H01L2224/0615 , H01L2224/371 , H01L2224/40245 , H01L2224/40499 , H01L2224/41113 , H01L2224/4117 , H01L2224/48247 , H01L2224/49113 , H01L2224/4917 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2224/03 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, a semiconductor assembly member, and a manufacturing method of the semiconductor device which easily manufacture various on-resistance elements.SOLUTION: A semiconductor device according to an embodiment includes element parts, first electrode parts, second electrode parts, and extended parts. The element parts are provided on a substrate. The first electrode parts are respectively provided on the element parts and establish electrical continuity with the element parts. The second electrode parts are respectively provided on the element parts so as to be spaced apart from the first electrode parts and establish electrical continuity with the element parts. The extended parts are provided on the element parts so as to extend from peripheral parts of the first electrode parts and the second electrode parts toward a peripheral part of the substrate.
摘要翻译：解决的问题：提供一种容易制造各种导通电阻元件的半导体器件，半导体组件和半导体器件的制造方法。解决方案：根据实施例的半导体器件包括元件部件，第一电极部件，第二电极部件和延伸部件。元件部件设置在基板上。第一电极部分分别设置在元件部件上并与元件部件建立电连续性。第二电极部分分别设置在元件部分上，以与第一电极部分间隔开，并与元件部分建立电连续性。延伸部分设置在元件部分上，以从第一电极部分和第二电极部分的周边部分延伸到基板的周边部分。版权所有（C）2012，JPO＆INPIT

122. 发明专利

JP2012094555A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012094555A
公开(公告)日：2012-05-17
申请号：JP2009035109
申请日：2009-02-18
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： YUYA NAOKI
IPC分类号： H01L21/336 , H01L21/28 , H01L29/12 , H01L29/78
CPC分类号： H01L21/0485 , H01L29/0649 , H01L29/0696 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that is capable of suppressing complication and lengthening of a manufacturing process and has excellent mass productivity.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a stacked film 19 on a gate electrode 7; and forming first contact holes 12 in which source regions 3 and p+ base/contact regions 5 are exposed from the bottoms of the first contact holes 12 and forming second contact holes 13 in which the stacked film 19 is exposed from the bottoms of the second contact holes 13 at the same time by applying an etching treatment to an interlayer insulating film 8 after the interlayer insulating film 8 is formed. The etching treatment is performed under the etching condition that the etching rate of the stacked film 19 is slower than that of the interlayer insulating film 8.
摘要翻译：解决的问题：提供能够抑制制造过程的复杂化和延长并且具有优异的批量生产率的半导体器件的制造方法。解决方案：制造半导体器件的方法包括以下步骤：在栅电极7上形成层叠膜19; 并且形成第一接触孔12，其中源极区域3和p +基极/接触区域5从第一接触孔12的底部露出，并形成第二接触孔13，其中层叠膜19从第二接触部的底部露出在层间绝缘膜8形成之后，通过对层间绝缘膜8进行蚀刻处理，同时进行通孔13。在层叠膜19的蚀刻速度比层间绝缘膜8的蚀刻速度慢的蚀刻条件下进行蚀刻处理。（C）2012，JPO＆INPIT

123. 发明专利

JP2012080135A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012080135A
公开(公告)日：2012-04-19
申请号：JP2012011533
申请日：2012-01-23
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KOBAYASHI TAKASHI , FUJIHIRA TATSUHIKO , ABE KAZU , NIIMURA YASUSHI , INOUE MASANORI
IPC分类号： H01L29/06 , H01L21/336 , H01L23/29 , H01L29/08 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7811 , H01L23/293 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/4238 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an MOS (Metal Oxide Semiconductor) semiconductor device, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and an IGBT (Insulated Gate Bipolar Transistor), and the like, that improves a trade-off relation between a withstanding voltage and an on-resistance of the MOS semiconductor device to realize a high withstanding voltage and a low on-resistance, and that enables high-speed switching.SOLUTION: A semiconductor device has: a first or second conductive type low resistance layer; a voltage supporting layer including at least first conductive type semiconductor region arranged on the low resistance layer; a second conductive type well region arranged on a surface layer of the voltage supporting layer; a plurality of second conductive type guard rings arranged so as to surround the second conductive type well region on the semiconductor surface. In the semiconductor device, an interval between the second conductive type well region and the second conductive type guard ring arranged at first counting from the second conductive type well region side, is 1 μm or less.
摘要翻译：要解决的问题：为了提供诸如MOSFET（金属氧化物半导体场效应晶体管）的MOS（金属氧化物半导体）半导体器件和IGBT（绝缘栅双极晶体管）等，其改善了抵消电压与MOS半导体器件的导通电阻之间的权衡关系，以实现高耐受电压和低导通电阻，并且能够进行高速切换。解决方案：半导体器件具有：第一或第二导电型低电阻层; 电压支撑层，其包括布置在所述低电阻层上的至少第一导电型半导体区域; 布置在电压支撑层的表面层上的第二导电类型阱区; 多个第二导电型保护环，其布置成围绕半导体表面上的第二导电类型阱区域。在半导体装置中，第一导电型阱区域和从第二导电型阱区域侧开始排列的第二导电型保护环之间的间隔为1μm以下。版权所有（C）2012，JPO＆INPIT

124. 发明专利

JP4913336B2 Semiconductor device 有权
公开(公告)号：JP4913336B2
公开(公告)日：2012-04-11
申请号：JP2004281002
申请日：2004-09-28
申请人：ルネサスエレクトロニクス株式会社
发明人：欣也大谷
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7804 , H01L29/7811
摘要： The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.

125. 发明专利

JP2012069991A Method of manufacturing superjunction device 审中-公开
标题翻译：制造超导装置的方法
公开(公告)号：JP2012069991A
公开(公告)日：2012-04-05
申请号：JP2011264063
申请日：2011-12-01
申请人： Third Dimension (3D) Semiconductor Inc , サードディメンジョン (スリーディ) セミコンダクタインコーポレイテッド
发明人： HSHIEH FWU-IUAN
IPC分类号： H01L29/78 , H01L21/265 , H01L21/266 , H01L21/336 , H01L21/76 , H01L29/06
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To provide an edge terminal with high voltage blocking capability in a semiconductor device.SOLUTION: A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, a mask is placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench are formed by etching through the oxide layer thereby forming mesas. The at least one second trench is deeper and wider than each of the plurality of first trenches. The device includes a second oxide layer positioned over an area of the mesas and the plurality of first trenches. The device includes a layer of a masking material that is deposited over the area of an edge terminal region adjacent to an active region. The area of mesas and the first trenches not covered by the masking layer are etched to remove oxidant seal. The device includes an overhang area formed by wet etching.
摘要翻译：要解决的问题：为了在半导体器件中提供具有高电压阻断能力的边沿端子。解决方案：部分制造的半导体器件包括半导体衬底。该器件包括形成在衬底上的第一氧化物层，掩模被放置在氧化物覆盖的衬底上，多个第一沟槽和至少一个第二沟槽通过蚀刻穿过氧化物层从而形成台面形成。所述至少一个第二沟槽比所述多个第一沟槽中的每一个更深和更宽。该装置包括位于台面和多个第一沟槽的区域上的第二氧化物层。该器件包括沉积在邻近有源区域的边缘端子区域的区域上的掩模材料层。蚀刻台面的区域和未被掩模层覆盖的第一沟槽以去除氧化剂密封。该装置包括通过湿蚀刻形成的悬垂区域。版权所有（C）2012，JPO＆INPIT

126. 发明专利

JP2012069838A Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：JP2012069838A
公开(公告)日：2012-04-05
申请号：JP2010214822
申请日：2010-09-27
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SAKANISHI KOICHIRO , KACHI TAKESHI , FUJISHIMA KOJI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06
CPC分类号： H01L29/66681 , H01L21/28079 , H01L21/32134 , H01L21/76841 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/495 , H01L29/66325 , H01L29/66719 , H01L29/66727 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To solve the problem of an isolated gate power semiconductor active element, that generally has many gate electrodes arranged in parallel with a stack of barrier metal films and thick aluminum-based electrode films over the gate electrodes with interlayer insulation films interposed therebetween, in which: voids may arise along with gate electrodes arranged in parallel to each other if aluminum-based electrode films are filled therebetween; and when wet etching is performed, any void may cause penetration of etchant therethrough and thus over etching of an active cell section where the aluminum-based electrode films should remain.SOLUTION: An isolated gate power semiconductor device includes: a plurality of gate electrodes provided so as to protrude outward from an active cell region; and a gate electrode coupling part for coupling the gate electrodes together at the active cell region, the top of the gate electrode coupling part being covered with a metal electrode covering the active cell region.
摘要翻译：要解决的问题：为了解决隔离栅极功率半导体有源元件的问题，其通常具有许多栅极电极，其平行布置在栅极电极上的阻挡金属膜和厚的铝基电极膜之间，具有中间层插入其间的绝缘膜，其中：如果在其间填充铝基电极膜，则可能与彼此平行布置的栅电极一起出现空隙; 并且当进行湿蚀刻时，任何空隙可能导致蚀刻剂穿透其中并因此导致蚀刻需要保留铝基电极膜的活性电池部分。解决方案：隔离栅极功率半导体器件包括：多个栅电极，设置成从有源电池区向外突出; 以及用于在有源单元区域将栅电极耦合在一起的栅电极耦合部分，栅电极耦合部分的顶部被覆盖有源电池区的金属电极覆盖。版权所有（C）2012，JPO＆INPIT

127. 发明专利

JP4907862B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP4907862B2
公开(公告)日：2012-04-04
申请号：JP2004358010
申请日：2004-12-10
申请人：ルネサスエレクトロニクス株式会社
发明人：喜直三浦 , 仁二宮
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/7808 , H01L29/7811
摘要： A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.

128. 发明专利

JP2012064899A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012064899A
公开(公告)日：2012-03-29
申请号：JP2010210134
申请日：2010-09-17
申请人： Toshiba Corp , 株式会社東芝
发明人： ONO SHOTARO , SAITO WATARU , TANIUCHI SHUNJI , WATANABE YOSHIO , YAMASHITA HIROAKI
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7811 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L29/0619 , H01L29/402 , H01L29/42372 , H01L29/66712 , H01L2224/40245 , H01L2224/40479 , H01L2224/40499 , H01L2224/4103 , H01L2224/84203 , H01L2924/00014 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2224/37099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing avalanche breakdown in a lower portion of a gate electrode pad and capable of utilizing a region under the gate electrode pad as a current channel.SOLUTION: A semiconductor device 100 comprises: main electrodes 12 electrically connected to a first semiconductor region 2 of a first conductive type and second semiconductor regions 3 selectively provided on a surface of the first semiconductor region; control electrodes 7 provided on the second semiconductor regions via a first insulating film; lead-out electrodes 13 electrically connected to the control electrodes; a second insulating film 15 provided on the main electrodes and the lead-out electrodes; and a plurality of contact electrodes 21 that are provided in a plurality of contact holes 15a formed in the second insulating film and are electrically connected to the lead-out electrodes. Control terminals, which are electrically insulated from the main electrodes by the second insulating film, are electrically connected to the plurality of contact electrodes.
摘要翻译：解决的问题：提供能够防止栅极电极焊盘的下部的雪崩击穿并且能够利用栅极电极焊盘下方的区域作为电流通道的半导体器件。解决方案：半导体器件100包括：电连接到第一导电类型的第一半导体区域2和选择性地设置在第一半导体区域的表面上的第二半导体区域3的主电极12; 通过第一绝缘膜设置在第二半导体区上的控制电极7; 电连接到控制电极的引出电极13; 设置在主电极和引出电极上的第二绝缘膜15; 以及多个接触电极21，其设置在形成在第二绝缘膜中并与引出电极电连接的多个接触孔15a中。通过第二绝缘膜与主电极电绝缘的控制端子电连接到多个接触电极。版权所有（C）2012，JPO＆INPIT

129. 发明专利

JP2012004312A Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件和硅碳化硅半导体器件的方法
公开(公告)号：JP2012004312A
公开(公告)日：2012-01-05
申请号：JP2010137539
申请日：2010-06-16
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MATSUKI HIDEO , SUGIMOTO MASAHIRO , TAKATANI HIDESHI , MORIMOTO ATSUSHI , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/1608 , H01L29/66068 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To simplify a manufacturing process by simplifying a step for forming a RESURF layer or an impurity layer constituting an EQR structure.SOLUTION: The surface layer of an n-type drift layer located below a recess 20 in a p-type RESURF layer 21 is connected, by migration of SiC, to a part formed on the surface layer of a p-type base region 3 in the p-type RESURF layer 21. Consequently, the p-type RESURF layer 21 can be connected to the p-type base region 3 without requiring oblique ion implantation even if the side wall of the recess 20 is steep. Since the step for forming the p-type RESURF layer 21 can be simplified, the manufacturing process can be simplified.
摘要翻译：解决的问题：为了简化制造工序，简化形成构成EQR结构的RESURF层或杂质层的工序。解决方案：通过SiC的迁移将位于p型RESURF层21中的凹部20下方的n

130. 发明专利

JP4844605B2 Semiconductor device 有权
公开(公告)号：JP4844605B2
公开(公告)日：2011-12-28
申请号：JP2008231781
申请日：2008-09-10
申请人：ソニー株式会社
发明人：有司佐々木
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/063 , H01L29/0696 , H01L29/1095 , H01L29/66712 , H01L29/7811

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