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1. 发明专利

JP2012033714A Semiconductor device, manufacturing method and packaging method thereof 有权
标题翻译：半导体器件，制造方法及其封装方法
公开(公告)号：JP2012033714A
公开(公告)日：2012-02-16
申请号：JP2010172022
申请日：2010-07-30
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： MOCHIZUKI EIJI , KOBAYASHI TAKASHI , KOBAYASHI HIDETO , KOYAMA MASAAKI
IPC分类号： H01L23/12 , H01L23/36 , H01L25/04 , H01L25/18 , H02M7/48
CPC分类号： H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To manufacture diverse, high-quality semiconductor devices efficiently.SOLUTION: A semiconductor device 1 comprises: a heat dissipating member 10; a wiring layer 20, formed on the heat dissipating member 10, including a circuit pattern 21 and an insulating layer 22 containing resin; and semiconductor elements 30 and 40, mounted on the wiring layer 20, containing electronic elements and sealing resin for sealing the electronic elements. A sealing process after packaging of the semiconductor elements 30 and 40 is not necessary, and also it is possible to efficiently obtain the semiconductor devices 1 with various functions by changing the circuit pattern 21 to be formed and the semiconductor elements 30 and 40 to be used.
摘要翻译：要解决的问题：有效地制造多样化，高质量的半导体器件。解决方案：半导体器件1包括：散热构件10; 形成在散热构件10上的布线层20，包括电路图案21和包含树脂的绝缘层22; 以及安装在布线层20上的包含用于密封电子元件的电子元件和密封树脂的半导体元件30和40。半导体元件30和40的封装之后的密封工艺不是必需的，并且通过改变要形成的电路图案21和要使用的半导体元件30和40，可以有效地获得具有各种功能的半导体器件1 。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2013084979A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013084979A
公开(公告)日：2013-05-09
申请号：JP2012284039
申请日：2012-12-27
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NISHIMURA TAKEYOSHI , KOBAYASHI TAKASHI , NIIMURA YASUSHI , YAMADA TADANORI
IPC分类号： H01L27/04 , H01L21/329 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/78 , H01L29/861 , H01L29/866 , H01L29/868
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving ESD resistance between a gate and a source without increasing on-state resistance.SOLUTION: A semiconductor device comprises structure of connecting in parallel zener diodes formed by using a polysilicon gate layer for improving ESD resistance, and the striped or rectangular zener diodes are connected in parallel to be each formed inside an active part.
摘要翻译：解决的问题：提供能够提高栅极和源极之间的ESD电阻而不增加导通电阻的半导体器件。解决方案：半导体器件包括通过使用多晶硅栅极层形成的并联齐纳二极管连接以提高ESD电阻的结构，并且条形或矩形齐纳二极管并联连接以形成在有源部分内部。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012129537A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012129537A
公开(公告)日：2012-07-05
申请号：JP2012021423
申请日：2012-02-03
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KOBAYASHI TAKASHI , SASAKI KOJI , MIKOSHIBA KOJI , KATO MASAHIRO
IPC分类号： H01L21/28 , H01L21/336 , H01L21/66 , H01L29/41 , H01L29/739 , H01L29/78
CPC分类号： H01L2924/13091
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which tends not to cause erroneous determination on a leakage current due to a piezoelectric effect at a chip formation place in a wafer state even when there are foreign particles on a stage for measuring characteristics.SOLUTION: In the case where a thickness of a rear face diffusion layer 16 including an n field stop layer 9 formed on the rear face side of an n semiconductor substrate 1 and a p collector layer 10 formed on the surface layer of the n field stop layer 9 is so thin as 5 μm and under, an erroneous determination rate of a leakage current of a chip in a wafer state due to a piezoelectric effect is decreased by creating a stress buffer obtained by inserting an Al-Si film 12 of 0.3 μm-4 μm into a multilayer film of Ti films 11, 13, an Ni film 14 and the like which form a rear face electrode 19.
摘要翻译：要解决的问题：提供一种半导体器件，其即使在用于测量特性的载物台上存在外来颗粒时，也不会因晶片状态的芯片形成位置处的压电效应而导致对漏电流的错误判定。解决方案：在形成在n半导体衬底1的背面侧的n场阻挡层9和形成在n的表面层上的p1集电极层10的背面扩散层16的厚度的情况下场阻止层9如此薄至5μm以下，由于压电效应导致的晶片状态的芯片的漏电流的错误判定率通过产生通过将Al-Si膜12插入 0.3μm〜4μm的Ti膜11,13的多层膜，形成背面电极19的Ni膜14等。（C）2012，JPO＆INPIT

4. 发明专利

JP2003338624A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2003338624A
公开(公告)日：2003-11-28
申请号：JP2002145902
申请日：2002-05-21
申请人： Fuji Electric Co Ltd , Natl Space Development Agency Of Japan , 宇宙開発事業団 , 富士電機株式会社
发明人： TAGAMI SABURO , KOBAYASHI TAKASHI , KIRIHATA FUMIAKI , KUBOYAMA TOMOJI
IPC分类号： H01L29/08 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0847 , H01L29/0878 , H01L29/7802 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a power MOSFET (metal oxide semiconductor field-effect transistor) having sufficient SEB (single event burnout) resistance used for space. SOLUTION: A second N base layer 3 and a first N - base layer 22 are epitaxially grown on a N + drain layer 21 successively, a P base region 23 is selectively formed on its surface, and a N + source region 24 is selectively formed on a surface in it. A gate electrode 26 is formed through a gate dielectric film 25 on a channel region, and a source electrode 27 is formed. A drain electrode 28 is formed on the back of a substrate. The thickness d2 of the second N base layer 3 is not less than 1/2 of a difference between the thickness d1 of the first N - base layer 22 and the thickness shown in VSEB(V)=8x (μm), and a mean impurity concentration is not less than 1×10 15 /cm 3 and not more than 3×10 17 /cm 3 , thereby positive feedback between latch-up in a parasitic npn transistor and a dynamic avalanche near the substrate is hard to break out and SEB resistance is improved. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供具有足够的用于空间的SEB（单事件烧尽）电阻的功率MOSFET（金属氧化物半导体场效应晶体管）。解决方案：第二N基极层3和第一N - / SP>基极层22依次在N + SP +漏极层21上外延生长，P基极区域23 在其表面上选择性地形成，并且在其表面上选择性地形成N + 源极区24。栅电极26通过沟道区上的栅极电介质膜25形成，形成源电极27。漏极电极28形成在衬底的背面。第二N基层3的厚度d2不小于第一N - / SP>基层22的厚度d1和VSEB（V）= 8x所示的厚度之差的1/2 （μm），平均杂质浓度为1×10 3 / SP 3以上3×10 3 / cm 3，因此寄生npn晶体管的闭锁与基板附近的动态雪崩之间的正反馈难以突破，并且提高了SEB电阻。版权所有（C）2004，JPO

5. 发明专利

JP2003008014A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2003008014A
公开(公告)日：2003-01-10
申请号：JP2001176500
申请日：2001-06-12
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KOBAYASHI TAKASHI , FUJIHIRA TATSUHIKO , ABE KAZU , NIIMURA YASUSHI , INOUE MASANORI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/739
CPC分类号： H01L29/0634
摘要： PROBLEM TO BE SOLVED: To provide a MOS semiconductor device, such as a MOSFET and an IGBT, which has high dielectric strength and low ON resistance and can switch at a high speed by improving the tradeoff relation between the dielectric strength and ON resistance of the MOS semiconductor device.
SOLUTION: The surface of an n
- surface area 14 as a surface exposed part of an n
- drift layer 12 with high specific resistance is striped while surrounded with a p well area 13 and the area ratio of the n
- surface area 14 to the p well area 13 including an n
+ source area 15 is 0.01 to 0.2. The number (n) of guard rings is ≥ withstand voltage Vbr(V)/100 and the intervals are, for example, ≤1 μm, or narrow.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供具有高介电强度和低导通电阻的诸如MOSFET和IGBT的MOS半导体器件，并且可以通过改善介电强度和导通电阻之间的折衷关系而以高速切换 MOS半导体器件。解决方案：作为具有高电阻率的n漂移层12的表面暴露部分的n <！ - SIPO - >表面积14的表面被条纹化，同时被p阱区域13包围，并且n < 包括n +源区域15的p阱区域13的表面积为0.01〜0.2。保护环的数量（n）为≥=耐电压Vbr（V）/ 100，间隔例如<=1μm或窄。

6. 发明专利

JP2002368215A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2002368215A
公开(公告)日：2002-12-20
申请号：JP2001176499
申请日：2001-06-12
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： FUJIHIRA TATSUHIKO , KOBAYASHI TAKASHI , ABE KAZU , NIIMURA YASUSHI , INOUE MASANORI
IPC分类号： H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/402 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has high dielectric strength and low ON-resistance, and can switch at a high speed by improviding the trade-off relation between the dielectric strength and the ON-resistance. SOLUTION: Resistivity p (Ω.cm) of a voltage base layer of a longitudinal semiconductor with a dielectric strength Vbr (V) lies in the range such that -5.34+0.0316 Vbf surface region 14 as the surface exposed part of an n drift layer 12 with high resistivity is striped, while surrounded with a p well region 13 and the region ratio of the n surface region 14 to the area of a p well area 13 including the n source region 15 is 0.01 to 0.2.
摘要翻译：要解决的问题：提供一种具有高介电强度和低导通电阻的半导体器件，并且通过改善介电强度和导通电阻之间的折衷关系，可以高速切换。解决方案：具有介电强度Vbr（V）的纵向半导体的电压基底层的电阻率p（Ω.cm）处于-5.34 + 0.0316Vbf <ρ<-1.86 + 0.0509Vbr的范围内。此外，作为具有高电阻率的n漂移层12的表面暴露部分的n +表面区域14的表面被条纹化，同时被p阱区域13包围，并且n < 表面区域14至包含n +源区域15的区域13的区域为0.01〜0.2。

7. 发明专利

JP2014042078A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014042078A
公开(公告)日：2014-03-06
申请号：JP2013249114
申请日：2013-12-02
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： SASAKI KOJI , MATSUZAKI KAZUO , KOBAYASHI TAKASHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/532
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having laminate metallic electrode wiring for improving the humidity-resistance of a section where barrier metal whose surface is a TiN film is exposed, and for eliminating a failure due to any crack even when a passivation film is formed as one layer, and for suppressing the increase of a failure due to the growth of an Si nodule in aluminum alloy and a method for manufacturing the semiconductor device.SOLUTION: This semiconductor device includes: a barrier metal film as a base and aluminum or an aluminum alloy film 2 laminated thereon; and an organic passivation film 7 coated on the aluminum or aluminum alloy film 2 as a metallic electrode wiring film formed with a required wiring pattern on a semiconductor substrate. The barrier metal film includes: a titanium nitride film 4; and a titanium film 9 being the uppermost surface laminated thereon, and the barrier metal film is extended from the aluminum or the aluminum alloy film 2, and the titanium film 9 on the uppermost surface of the extended barrier metal film is coated with the organic passivation film 7.
摘要翻译：要解决的问题：提供一种半导体器件，其具有用于提高其表面为TiN膜的阻挡金属被暴露的部分的耐湿性的叠层金属电极布线，并且即使当钝化膜形成为一层，并且用于抑制由于铝合金中的Si结块的生长引起的故障的增加以及半导体器件的制造方法。解决方案：该半导体器件包括：作为基底的阻挡金属膜和铝或层压在其上的铝合金膜2; 以及涂覆在铝或铝合金膜2上的有机钝化膜7作为在半导体衬底上形成所需布线图案的金属电极布线膜。阻挡金属膜包括：氮化钛膜4; 并且层压在其上的最上表面的钛膜9，并且阻挡金属膜从铝或铝合金膜2延伸，并且延伸的阻挡金属膜的最上表面上的钛膜9涂覆有机钝化电影7。

8. 发明专利

JP2012080135A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012080135A
公开(公告)日：2012-04-19
申请号：JP2012011533
申请日：2012-01-23
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KOBAYASHI TAKASHI , FUJIHIRA TATSUHIKO , ABE KAZU , NIIMURA YASUSHI , INOUE MASANORI
IPC分类号： H01L29/06 , H01L21/336 , H01L23/29 , H01L29/08 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7811 , H01L23/293 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/4238 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an MOS (Metal Oxide Semiconductor) semiconductor device, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and an IGBT (Insulated Gate Bipolar Transistor), and the like, that improves a trade-off relation between a withstanding voltage and an on-resistance of the MOS semiconductor device to realize a high withstanding voltage and a low on-resistance, and that enables high-speed switching.SOLUTION: A semiconductor device has: a first or second conductive type low resistance layer; a voltage supporting layer including at least first conductive type semiconductor region arranged on the low resistance layer; a second conductive type well region arranged on a surface layer of the voltage supporting layer; a plurality of second conductive type guard rings arranged so as to surround the second conductive type well region on the semiconductor surface. In the semiconductor device, an interval between the second conductive type well region and the second conductive type guard ring arranged at first counting from the second conductive type well region side, is 1 μm or less.
摘要翻译：要解决的问题：为了提供诸如MOSFET（金属氧化物半导体场效应晶体管）的MOS（金属氧化物半导体）半导体器件和IGBT（绝缘栅双极晶体管）等，其改善了抵消电压与MOS半导体器件的导通电阻之间的权衡关系，以实现高耐受电压和低导通电阻，并且能够进行高速切换。解决方案：半导体器件具有：第一或第二导电型低电阻层; 电压支撑层，其包括布置在所述低电阻层上的至少第一导电型半导体区域; 布置在电压支撑层的表面层上的第二导电类型阱区; 多个第二导电型保护环，其布置成围绕半导体表面上的第二导电类型阱区域。在半导体装置中，第一导电型阱区域和从第二导电型阱区域侧开始排列的第二导电型保护环之间的间隔为1μm以下。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JPH08139316A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08139316A
公开(公告)日：1996-05-31
申请号：JP27619594
申请日：1994-11-10
申请人： FUJI ELECTRIC CO LTD
发明人： FUJIHIRA TATSUHIKO , MOMOTA SEIJI , NISHIMURA TAKEYOSHI , SUGIMURA KAZUTOSHI , YOSHINO MASAO , KOBAYASHI TAKASHI
IPC分类号： H01L21/28 , H01L21/265 , H01L21/266 , H01L21/306 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L29/78
摘要： PURPOSE: To eliminate one photo process by opening windows at the same time for contact holes at the places where the film thicknesses of oxide films are different by opening the windows while confirming in etching monitor regions instead of the conventional process in which a high-concentration n-layer was formed by the ion-implantation of arsenic by using photoresist as mask. CONSTITUTION: Ion-implantation of arsenic is performed and n region 9 is formed by using a second insulation film 7 formed on a semiconductor wafer and a gate electrode 8 formed by polysilicon as mask. Also, to form a contact hole 11, the contact hole 11 above a p-region 5 covered by a fourth insulation film 10 and a second insulation film 3 and the contact hole 11 above n region 9 covered by a fourth insulation film are formed simultaneously by etching while monitoring a monitor region.

10. 发明专利

JP2003163350A MOS SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003163350A
公开(公告)日：2003-06-06
申请号：JP2002297621
申请日：2002-10-10
申请人： FUJI ELECTRIC CO LTD
发明人： FUJIHIRA TATSUHIKO , NISHIMURA TAKEYOSHI , KOBAYASHI TAKASHI
IPC分类号： H01L29/749 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To enhance breakdown voltage and avalanche resistance by preventing concentration of avalanche current to a corner of the channel region of cell structure of an FET having a square second conductivity channel region in the surface layer of a first conductivity semiconductor substrate, a heavily doped well region in the central part thereof, a first conductivity source region in the surface layer, and an MOS structure on the surface. SOLUTION: One side of the square channel region of a cell structure is linked with one side of an adjacent channel region. For example, an angular projecting part of the channel region is eliminated by interlinking the short sides of rectangular channel regions and avalanche resistance is enhanced because concentration of avalanche current to a corner part is eliminated. At the outermost circumferential part arranged with the cell structures of a semiconductor chip, an outermost circumferential cell structure 19 where the outer side of the channel region of a cell structure is parallel with the side of the semiconductor chip, and an outer cell structure 20 where the outer side of the channel region is rendered arcuate toward the corner of the semiconductor chip, are provided. Since the curvature of the outermost circumferential pn junction decreases, concentration of field is retarded and avalanche resistance is enhanced. COPYRIGHT: (C)2003,JPO

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