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111. 发明专利

JP2013533628A Three-dimensional memory and a method of forming the same 有权
公开(公告)号：JP2013533628A
公开(公告)日：2013-08-22
申请号：JP2013518511
申请日：2011-06-24
申请人：マイクロンテクノロジー, インク.
发明人：ディー．タン，サン , ケー．ザフラク，ジョン
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L45/00 , H01L49/00
CPC分类号： H01L27/11582 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2213/71 , H01L21/28273 , H01L21/76838 , H01L23/528 , H01L27/0688 , H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/06
摘要：一部の実施形態は、メモリデバイス、およびそのメモリデバイスの形成方法を含む。１つのそのようなメモリデバイスは、メモリセルの第１のグループを含み、この第１のグループの各メモリセルは、そのメモリデバイスの１つのデバイスレベル内に配置される第１の制御ゲートの、空洞内に形成される。このメモリデバイスはまた、メモリセルの第２のグループも含み、この第２のグループの各メモリセルは、そのメモリデバイスの別のデバイスレベル内に配置される第２の制御ゲートの、空洞内に形成される。追加的な装置および方法が説明される。
【選択図】図３

112. 发明专利

JP2013069831A Manufacturing method of nonvolatile semiconductor storage device and nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件和非易失性半导体存储器件的制造方法
公开(公告)号：JP2013069831A
公开(公告)日：2013-04-18
申请号：JP2011206893
申请日：2011-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SATO MITSURU , ISHIZUKI MEGUMI , KITO MASARU , KONNO ATSUSHI , AKUTSU YOSHIHIRO , KITO TAKASHI , FUKUZUMI YOSHIAKI , KATSUMATA RYUTA
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , H01L21/265 , H01L27/11582 , H01L29/0676 , H01L29/66833
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a nonvolatile semiconductor storage device and the nonvolatile semiconductor storage device which improve controllability of memory cells.SOLUTION: A manufacturing method of a nonvolatile semiconductor storage device comprises the steps of: forming a first laminate and a second laminate on a substrate; forming a through hole passing through the first laminate and the second laminate; forming a memory film on a side wall of a first portion of the through hole, gate insulating films on side walls of a second portion and a third portion of the through hole and channel bodies inside the memory film and the gate insulating films; forming a third insulating layer containing silicon oxide inside the channel bodies and blocking a boundary portion between the second portion and the third portion by the third insulating layer; forming a first embedding portion containing silicon inside the third portion; removing a part of the first embedding portion and a part of the third insulating layer and exposing the channel bodies; and embedding a second embedding portion containing the silicon having impurity concentration higher than that of the first embedding portion on the first embedding portion in an inside of the third portion.
摘要翻译：解决的问题：提供一种提高存储单元的可控性的非易失性半导体存储装置和非易失性半导体存储装置的制造方法。解决方案：非易失性半导体存储器件的制造方法包括以下步骤：在衬底上形成第一层压体和第二层压体; 形成通过所述第一层压体和所述第二层压体的通孔; 在通孔的第一部分的侧壁上形成记忆膜，在第二部分的侧壁上的栅极绝缘膜和通孔的第三部分以及存储膜内的通道体和栅极绝缘膜; 在所述通道体内形成含有氧化硅的第三绝缘层，并且通过所述第三绝缘层阻挡所述第二部分和所述第三部分之间的边界部分; 在第三部分内形成含有硅的第一嵌入部分; 去除所述第一嵌入部分的一部分和所述第三绝缘层的一部分并暴露所述通道体; 以及在第三部分的内部将包含杂质浓度高于第一嵌入部分的硅的第二嵌入部分嵌入在第一嵌入部分上。版权所有（C）2013，JPO＆INPIT

113. 发明专利

JP2013069751A Nonvolatile semiconductor storage device and manufacturing method of the same 审中-公开
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2013069751A
公开(公告)日：2013-04-18
申请号：JP2011205752
申请日：2011-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： MORI SHINJI
IPC分类号： H01L21/8247 , C23C16/42 , C23C16/56 , H01L21/205 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , H01L21/02532 , H01L21/0262 , H01L27/11582 , H01L29/66833
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device and a manufacturing method of the same which improve channel mobility.SOLUTION: A nonvolatile semiconductor storage device comprises a memory transistor 40 and a selection transistor 50 which are provided on a semiconductor substrate 20. The memory transistor 40 includes conductive layers 41a-41d, a memory gate insulation layer 43, a columnar semiconductor layer 44 and an oxide layer 45. The conductive layer 41 functions as a gate of the memory transistor 40. The memory gate insulation layer 43 contacts lateral faces of the conductive layer. The semiconductor layer 44 sandwiches the memory gate insulation layer 43 by one lateral face together with the conductive layer and extends in a direction perpendicular to the semiconductor substrate 20. The semiconductor layer 44 functions as a body of the memory transistor 40. The oxide layer 45 contacts another lateral face of the semiconductor layer 44. The semiconductor layer 44 is composed of silicon germanium. The oxide layer 45 is composed of silicon oxide.
摘要翻译：解决的问题：提供一种提高信道移动性的非易失性半导体存储装置及其制造方法。解决方案：非易失性半导体存储器件包括设置在半导体衬底20上的存储晶体管40和选择晶体管50.存储晶体管40包括导电层41a-41d，存储栅极绝缘层43，柱状半导体层44和氧化物层45.导电层41用作存储晶体管40的栅极。存储器栅极绝缘层43接触导电层的侧面。半导体层44与导电层一起由一个侧面将存储器栅极绝缘层43夹持，并且在垂直于半导体衬底20的方向上延伸。半导体层44用作存储晶体管40的主体。氧化物层45 接触半导体层44的另一个侧面。半导体层44由硅锗构成。氧化物层45由氧化硅构成。版权所有（C）2013，JPO＆INPIT

114. 发明专利

JP5112201B2 Non-volatile semiconductor memory device 有权
公开(公告)号：JP5112201B2
公开(公告)日：2013-01-09
申请号：JP2008181084
申请日：2008-07-11
申请人：株式会社東芝
发明人：嘉晃福住 , 英明青地 , 竜太勝又 , 傑鬼頭 , 大木藤 , 啓安田中 , 陽介小森 , 恵石月
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , G11C16/0466 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： A nonvolatile semiconductor memory device includes: a stacked body in which insulating films and electrode films are alternately stacked; selection gate electrodes provided on the stacked body; bit lines provided on the selection gate electrodes; semiconductor pillars; connective members separated from one another; and a charge storage layer provided between the electrode film and the semiconductor pillar. One of the connective members is connected between a lower part of one of the semiconductor pillars and a lower part of another of the semiconductor pillars. The one of the semiconductor pillars passes through one of the selection gate electrodes and is connected to one of the bit lines, and the another of the semiconductor pillars passes through another of the selection gate electrodes and is connected to another of the bit lines.

115. 发明专利

JP2012248691A Non-volatile semiconductor storage device and method of manufacturing the same 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2012248691A
公开(公告)日：2012-12-13
申请号：JP2011119467
申请日：2011-05-27
申请人： Toshiba Corp , 株式会社東芝
发明人： TORAYA KENICHIRO , TANAKA MASAYUKI , MATSUO KAZUNORI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28282 , H01L27/11568 , H01L27/11582 , H01L29/4234 , H01L29/66833 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device and a method of manufacturing the same capable of improving insulating characteristics of a memory cell.SOLUTION: A non-volatile semiconductor storage device according to an embodiment comprises a semiconductor region. An interface region containing a metallic element is provided on a surface of the semiconductor region. A tunnel insulating film is provided on a surface of the interface region. A charge accumulation insulating film is provided on a surface of the tunnel insulating film. A block insulating film is provided on a surface of the charge accumulation insulating film. A control gate electrode is provided on a surface of the block insulating film.
摘要翻译：要解决的问题：提供一种能够提高存储单元的绝缘特性的非易失性半导体存储装置及其制造方法。解决方案：根据实施例的非易失性半导体存储器件包括半导体区域。在半导体区域的表面上设置有包含金属元素的界面区域。隧道绝缘膜设置在界面区域的表面上。电荷累积绝缘膜设置在隧道绝缘膜的表面上。在电荷累积绝缘膜的表面上设置有块绝缘膜。控制栅电极设置在块绝缘膜的表面上。版权所有（C）2013，JPO＆INPIT

116. 发明专利

JP5091526B2 Semiconductor memory device and a method of manufacturing the same 有权
公开(公告)号：JP5091526B2
公开(公告)日：2012-12-05
申请号：JP2007100086
申请日：2007-04-06
申请人：株式会社東芝
发明人：啓安田中 , 竜太勝又 , 英明青地 , 大木藤 , 傑鬼頭 , 充佐藤
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/7881 , H01L29/7926
摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

117. 发明专利

JP5086959B2 Non-volatile semiconductor memory device 有权
公开(公告)号：JP5086959B2
公开(公告)日：2012-11-28
申请号：JP2008248350
申请日：2008-09-26
申请人：株式会社東芝
发明人：清太郎板垣 , 佳久岩田 , 傑鬼頭 , 英明青地 , 竜太勝又 , 晃寛仁田山 , 大木藤 , 啓安田中
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1157 , G11C5/02 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/7926
摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

118. 发明专利

JP2012204592A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2012204592A
公开(公告)日：2012-10-22
申请号：JP2011067633
申请日：2011-03-25
申请人： Toshiba Corp , 株式会社東芝
发明人： SHINOHARA HIROSHI , ICHINOSE DAIGO
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method which can form a structure in which bottom edges of memory strings are connected through less number of processes.SOLUTION: According to an embodiment, a semiconductor device manufacturing method comprises: a process of selectively injecting an impurity into a ground layer containing silicon by using a mask to form a boron additive region containing boron and an etching target region having a boron concentration lower than that of the boron additive region in the ground layer; a process of forming, in a laminate including a plurality of electrode layers, a pair of holes reaching the etching target region; and a process of removing the etching target region by using an etchant through the holes to form a recess in the ground layer, which is linked with bottom edges of the pair of holes.
摘要翻译：要解决的问题：提供一种半导体制造方法，其可以形成通过较少数量的工艺连接存储器串的底部边缘的结构。解决方案：根据实施例，半导体器件制造方法包括：通过使用掩模将杂质选择性地注入含硅的接地层中以形成含硼的硼添加剂区域和具有硼的蚀刻目标区域的工艺浓度低于地层中硼添加剂区域的浓度; 在包括多个电极层的层叠体中形成到达所述蚀刻对象区域的一对孔的工序; 以及通过使用蚀刻剂通过孔去除蚀刻目标区域的过程，以在与该一对孔的底部边缘连接的接地层中形成凹部。版权所有（C）2013，JPO＆INPIT

119. 发明专利

JP2012146350A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012146350A
公开(公告)日：2012-08-02
申请号：JP2011002028
申请日：2011-01-07
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUCHI NATSUKI , MAEDA TAKASHI
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To reduce area.SOLUTION: A nonvolatile semiconductor memory device includes a plurality of memory strings 200. Each of the memory strings includes a pair of columnar parts A; a semiconductor layer SP having a coupling part B formed to couple lower ends of the pair of columnar parts; a control gate CG which is orthogonal to the columnar parts; a first selection gate SGS which is orthogonal to one of the pair of columnar parts and formed above the control gate; a second selection gate SGD which is orthogonal to the other of the pair of columnar parts, formed above the control gate, and is integral with the first selection gate at the same level; a memory cell transistor MTr which is formed at each of intersections of the columnar parts and the control gate; a first selection transistor SSTr which is formed at each of intersections of the columnar parts and the first selection gate; and a second selection transistor SDTr which is formed at each of intersections of the columnar parts and the second selection gate.
摘要翻译：要解决的问题：减少面积。解决方案：非易失性半导体存储器件包括多个存储器串200.每个存储器串包括一对柱状部分A; 半导体层SP，具有形成为耦合所述一对柱状部分的下端的耦合部分B; 与柱状部分正交的控制栅极CG; 第一选择栅SGS，其与所述一对柱状部中的一个正交，并形成在所述控制栅上; 第二选择栅极SGD，其与所述一对柱状部分中的另一个正交，形成在所述控制栅极上方，并且与所述第一选择栅极在同一电平上成一体; 存储单元晶体管MTr，其形成在柱状部分和控制栅极的每个交点处; 第一选择晶体管SSTr，其形成在柱状部分和第一选择栅极的每个交点处; 以及形成在柱状部分和第二选择栅极的每个交点处的第二选择晶体管SDTr。版权所有（C）2012，JPO＆INPIT

120. 发明专利

JP4964378B2 The nonvolatile semiconductor memory device 有权
公开(公告)号：JP4964378B2
公开(公告)日：2012-06-27
申请号：JP2001520466
申请日：2000-08-25
申请人：マクロニックス・アメリカ・インコーポレーテッド
发明人：ラング，シャン・ラン , ル，タオ・チェン , ワン，マム・ツン
IPC分类号： G11C16/02 , H01L29/792 , G11C16/04 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/7923 , H01L29/7926

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