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1. 发明专利

JP2010087337A Nand type flash memory and method of manufacturing soi substrate 审中-公开
标题翻译： NAND型闪存及制造SOI衬底的方法
公开(公告)号：JP2010087337A
公开(公告)日：2010-04-15
申请号：JP2008256175
申请日：2008-10-01
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUMOTO ATSUYUKI , AISO NORIKI , ISHIDA KOICHI , OZAWA YOSHIO , MIZUKAMI MAKOTO , NISHIHARA KIYOHITO , ICHINOSE DAIGO , IGUCHI SUNAO
IPC分类号： H01L21/8247 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a NAND type flash memory that can improve characteristics of a memory cell. SOLUTION: The NAND type flash memory 100 includes: a silicon substrate; seed layers of the same conductivity type as the silicon substrate which are formed on the silicon substrate while extending in a first direction and each of which has a section in an isosceles trapezoid shape whose bottom is longer than the top, the section being along a plane perpendicular to the first direction; buried insulating films which are formed on the silicon substrate between the seed layers, a semiconductor layer formed on the seed layers and buried insulating films and are grown through solid-phase epitaxial growth; a plurality of floating gate electrode layers which are formed on the first gate insulating film between a first selection gate electrode layer and a second selection gate electrode layer and are arrayed in a second direction crossing the first direction on a substrate surface of the silicon substrate; second gate insulating films formed on the floating gate layers; and control gate electrode layers formed on the second gate insulating films. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供可以改善存储器单元的特性的NAND型闪速存储器。解决方案：NAND型闪速存储器100包括：硅衬底; 形成在硅基板上的与硅基板相同的导电类型的种子层在第一方向上延伸并且每个具有底部比顶部更长的等腰梯形形状的截面，该截面沿着平面垂直于第一方向; 形成在种子层之间的硅衬底上的埋入绝缘膜，形成在种子层上的半导体层和埋入的绝缘膜，并通过固相外延生长生长; 在第一选择栅极电极层和第二选择栅极电极层之间的第一栅极绝缘膜上形成的多个浮栅电极层，并且在与硅衬底的衬底表面上沿第一方向交叉的第二方向上排列; 形成在浮栅层上的第二栅极绝缘膜; 以及形成在第二栅极绝缘膜上的控制栅电极层。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2011108921A Non-volatile semiconductor memory device, and method for manufacturing the same 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2011108921A
公开(公告)日：2011-06-02
申请号：JP2009263830
申请日：2009-11-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ICHINOSE DAIGO , IGUCHI SUNAO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/11575 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device with uniform characteristics of memory cell transistors, and to provide a method for manufacturing the same. SOLUTION: A laminate 20 is formed on a silicon substrate 11 by repeating a step of depositing a boron-doped silicon layer 72, forming a silicon nitride layer 78 on the top surface thereof, depositing a non-doped silicon layer 73, and forming a silicon nitride layer 79 on the top surface of the non-doped silicon layer. Next, through holes 30a are formed in the laminate 20, and a sacrificial material is buried in the through holes to form slits 74 extending in the X direction in the laminate 20. Then, an etching solution is supplied into the slits 74 to remove the non-doped silicon layers 73 by wet etching. Then, the etching solution is removed, and an insulating material is buried between the boron-doped silicon layers 72 and in the slits 74. Then, the sacrificial reagent is removed from inside the through holes, and a charge storing film is formed on the inner surfaces thereof to form silicon pillars inside the through holes. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有均匀特性的存储单元晶体管的非易失性半导体存储器件，并提供其制造方法。解决方案：通过重复沉积硼掺杂硅层72，在其顶表面上形成氮化硅层78，沉积非掺杂硅层73的步骤，在硅衬底11上形成层压体20，以及在非掺杂硅层的顶表面上形成氮化硅层79。接下来，在层压体20中形成贯通孔30a，将牺牲材料埋设在通孔中，形成在层叠体20中沿X方向延伸的狭缝74.然后，将蚀刻液供给到狭缝74中，非掺杂硅层73。然后，去除蚀刻溶液，并且在硼掺杂硅层72和狭缝74之间埋设绝缘材料。然后，从通孔内部去除牺牲试剂，并且在其内表面在通孔内形成硅柱。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2014187191A Semiconductor storage device manufacturing method and semiconductor storage device 审中-公开
标题翻译：半导体存储器件制造方法和半导体存储器件
公开(公告)号：JP2014187191A
公开(公告)日：2014-10-02
申请号：JP2013061112
申请日：2013-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKAMURA KAZUHIDE , KATSUMATA RYUTA , KITO MASARU , UOZUMI NOBUHIRO , ICHINOSE DAIGO , MATSUDA TORU
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/8221 , H01L27/1157 , H01L27/11582 , H01L27/1214 , H01L29/792 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device manufacturing method and a semiconductor storage device, which enable appropriate and highly efficient processing on a laminate having a plurality of electrode films and a plurality of insulation films.SOLUTION: According to an embodiment, a semiconductor storage device manufacturing method comprises: a process of forming on a second stopper film, a laminate having a plurality of electrode films and a plurality of insulation films each provided between the plurality of electrode films; a process of forming in the laminate, slits which reach the second stopper film; a process of forming in the laminate, holes which pierces the laminate and the opening to reach the first stopper film; a process of removing the sacrificial film through the holes; a process of forming on sidewalls of the holes, memory films including charge storage films; and a process of forming channel bodies on sidewalls of the memory films. Each of the first stopper film and the second stopper film has etching resistance higher than that of each of the electrode film and the insulation film.
摘要翻译：要解决的问题：提供一种能够对具有多个电极膜和多个绝缘膜的层叠体进行适当且高效的处理的半导体存储装置制造方法和半导体存储装置。解决方案根据一个实施方案，半导体存储器件制造方法包括：在第二阻挡膜上形成具有多个电极膜的层压体和设置在所述多个电极膜之间的多个绝缘膜的工序; 在层叠体中形成到达第二止挡膜的狭缝的过程; 在层叠体中形成的方法，刺穿层压体的孔和开口以到达第一阻挡膜; 通过孔去除牺牲膜的工艺; 在孔的侧壁上形成的过程，包括电荷存储膜的记忆膜; 以及在存储膜的侧壁上形成通道体的工艺。第一阻挡膜和第二阻挡膜中的每一个具有高于每个电极膜和绝缘膜的耐腐蚀性。

4. 发明专利

JP2013065693A Manufacturing method of nonvolatile semiconductor storage device and nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件和非易失性半导体存储器件的制造方法
公开(公告)号：JP2013065693A
公开(公告)日：2013-04-11
申请号：JP2011203418
申请日：2011-09-16
申请人： Toshiba Corp , 株式会社東芝
发明人： ICHINOSE DAIGO , ISHIHARA HANAE
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To improve processing accuracy of a nonvolatile semiconductor storage device.SOLUTION: According to an embodiment, a manufacturing method of a nonvolatile semiconductor storage device comprises: forming a semiconductor layer having an impurity containing region and an etching target region; forming a first insulation layer from the surfaces to the insides of the regions; forming a laminate including a plurality of electrode layers on the semiconductor layer via the first insulation film; forming a pair of holes on the laminate, which reach the etching target region and sandwich a second insulation layer; removing the etching target region through the pair of holes to form, in the semiconductor layer, a space connected to bottom ends of the pair of holes; forming a memory film on a side wall of each of the pair of holes; forming a fourth insulation layer on an inner wall of the space; and forming a channel body layer on a surface of the memory film formed on the side wall of each of the pair of holes and the inner wall of the space.
摘要翻译：解决的问题：提高非易失性半导体存储装置的处理精度。解决方案：根据实施例，非易失性半导体存储装置的制造方法包括：形成具有杂质含量区域和蚀刻目标区域的半导体层; 从所述表面到所述区域的内部形成第一绝缘层; 通过所述第一绝缘膜在所述半导体层上形成包括多个电极层的层压体; 在层叠体上形成一对孔，到达蚀刻目标区域并夹着第二绝缘层; 通过所述一对孔去除所述蚀刻目标区域，以在所述半导体层中形成连接到所述一对孔的底端的空间; 在所述一对孔中的每一个的侧壁上形成记忆膜; 在所述空间的内壁上形成第四绝缘层; 以及在形成在所述一对孔的每一个的侧壁和所述空间的内壁上的所述记忆膜的表面上形成通道体层。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2012174887A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2012174887A
公开(公告)日：2012-09-10
申请号：JP2011035566
申请日：2011-02-22
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMORI YOSUKE , ICHINOSE DAIGO
IPC分类号： H01L29/792 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L29/7926 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device with high operation speed.SOLUTION: A semiconductor storage device according to an embodiment comprises: a plurality of gate electrode films arranged in parallel to one another along a certain direction; a semiconductor member extending along the certain direction and penetrating through the gate electrode films; and a charge accumulation film provided between the gate electrode films and the semiconductor member. A convex portion which projects along the certain direction is provided at an end portion opposite to the semiconductor member in the gate electrode film, and a layer of gas is formed in a part of space between the gate electrode films.
摘要翻译：要解决的问题：提供具有高操作速度的半导体存储装置。解决方案：根据实施例的半导体存储装置包括：沿着某个方向彼此平行布置的多个栅极电极膜; 沿该特定方向延伸并穿过栅极电极膜的半导体部件; 以及设置在栅极电极膜和半导体部件之间的电荷蓄积膜。在栅极电极膜的与半导体部件相反的端部设置有沿着该一定方向突出的凸部，并且在栅电极膜之间的空间的一部分中形成有气体层。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2012204592A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2012204592A
公开(公告)日：2012-10-22
申请号：JP2011067633
申请日：2011-03-25
申请人： Toshiba Corp , 株式会社東芝
发明人： SHINOHARA HIROSHI , ICHINOSE DAIGO
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method which can form a structure in which bottom edges of memory strings are connected through less number of processes.SOLUTION: According to an embodiment, a semiconductor device manufacturing method comprises: a process of selectively injecting an impurity into a ground layer containing silicon by using a mask to form a boron additive region containing boron and an etching target region having a boron concentration lower than that of the boron additive region in the ground layer; a process of forming, in a laminate including a plurality of electrode layers, a pair of holes reaching the etching target region; and a process of removing the etching target region by using an etchant through the holes to form a recess in the ground layer, which is linked with bottom edges of the pair of holes.
摘要翻译：要解决的问题：提供一种半导体制造方法，其可以形成通过较少数量的工艺连接存储器串的底部边缘的结构。解决方案：根据实施例，半导体器件制造方法包括：通过使用掩模将杂质选择性地注入含硅的接地层中以形成含硼的硼添加剂区域和具有硼的蚀刻目标区域的工艺浓度低于地层中硼添加剂区域的浓度; 在包括多个电极层的层叠体中形成到达所述蚀刻对象区域的一对孔的工序; 以及通过使用蚀刻剂通过孔去除蚀刻目标区域的过程，以在与该一对孔的底部边缘连接的接地层中形成凹部。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2010114380A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010114380A
公开(公告)日：2010-05-20
申请号：JP2008288010
申请日：2008-11-10
申请人： Toshiba Corp , 株式会社東芝
发明人： MIZUKAMI MAKOTO , NISHIHARA KIYOHITO , KONDO MASAKI , IZUMIDA TAKASHI , AISO NORIKI , ISHIDA KOICHI , FUKUMOTO ATSUYUKI , ICHINOSE DAIGO , IGUCHI SUNAO
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/20 , H01L21/3205 , H01L21/762 , H01L21/768 , H01L23/52 , H01L23/522 , H01L27/115 , H01L27/12 , H01L29/417 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has low contact resistance.
SOLUTION: The semiconductor device is constituted on an SOI (Silicon On Insulator) substrate having a semiconductor substrate of a first conductivity type, a buried oxide film, and a semiconductor layer of a second conductivity type. The buried oxide film has a first opening formed in itself to communicate the semiconductor substrate and semiconductor layer with each other. The semiconductor substrate has a connection layer of a second conductivity type formed while buried in a surface portion thereof and electrically connecting with the buried portion of the semiconductor layer in the first opening, and further includes a contact electrode which is buried in a second opening penetrating the semiconductor layer and buried oxide film to reach the surface portion of the connection layer and is electrically connected with the semiconductor layer on a side surface and is electrically connected with the connection layer on a bottom.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有低接触电阻的半导体器件。解决方案：半导体器件被构造在具有第一导电类型的半导体衬底，掩埋氧化物膜和第二导电类型的半导体层的SOI（绝缘体上硅）衬底上。埋入氧化物膜具有自身形成为使半导体衬底和半导体层彼此连通的第一开口。半导体衬底具有第二导电类型的连接层，同时埋入其表面部分并与第一开口中的半导体层的掩埋部分电连接，并且还包括接触电极，该接触电极被埋在第二开口中半导体层和埋入氧化膜到达连接层的表面部分并且在侧表面上与半导体层电连接并且在底部上与连接层电连接。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009278039A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009278039A
公开(公告)日：2009-11-26
申请号：JP2008130568
申请日：2008-05-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ICHINOSE DAIGO , IGUCHI SUNAO
IPC分类号： H01L21/3065 , H01L21/027 , H01L21/3213
CPC分类号： H01L21/0337 , H01L21/0338
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of forming a pattern including a fine line and space pattern accurately. SOLUTION: The method of manufacturing the semiconductor device includes a step of forming a core material on a processed material, a step of forming a coating film formed of amorphous material to cover an upper surface and side surface of the core material, a step of forming a sidewall mask on a sidewall of the core material by removing the coating film while remaining a part positioned on the side surface of the core material, a step of crystallizing the coating film before or after processing into the sidewall mask by carrying out thermal treatment before or after forming the sidewall mask from the coating film, a step of removing the core material after crystallizing the coating film before or after forming the sidewall mask and processing into the sidewall mask, a step of etching the processed material by using the sidewall mask as a mask after removing the core material. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种能够精确地形成包括细线和空间图案的图案的半导体器件的制造方法。解决方案：制造半导体器件的方法包括在被处理材料上形成芯材的步骤，形成由非晶材料形成的涂膜以覆盖芯材的上表面和侧表面的步骤，通过在保留位于芯材的侧表面上的部分的同时移除涂膜而在芯材的侧壁上形成侧壁掩模的步骤;通过执行在侧壁掩模加工之前或之后使涂膜结晶的步骤在从所述涂膜形成所述侧壁掩模之前或之后进行热处理，在形成所述侧壁掩模之前或之后，在所述涂膜结晶之后除去所述芯材料并加工到所述侧壁掩模中的步骤，通过使用所述侧壁掩模蚀刻所述加工材料的步骤去除芯材后将侧壁面罩作为掩模。版权所有（C）2010，JPO＆INPIT

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