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91. 发明专利

JPS5917784A Automatic gain control circuit 失效
标题翻译：自动增益控制电路
公开(公告)号：JPS5917784A
公开(公告)日：1984-01-30
申请号：JP12578782
申请日：1982-07-21
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： OKADA YOSHINORI , NAKAGAWA HIMIO , FURUHATA MAKOTO , MORI TAKAYUKI
IPC分类号： H04N5/53 , H04N5/91
CPC分类号： H04N5/91
摘要： PURPOSE:To make it difficult to generate a malfunction when the pulse width of a synchronizing signal generated from a separating circuit is narrower than a prescribed value, by providing an LPF and a comparing amplifier between the synchronizing signal separating circuit and a delay pulse generator. CONSTITUTION:A synchronizing signal 11 generated from a synchronizing signal separating circuit 10 becomes a signal 29 through an LPF26. This signal 29 is compared with a voltage 30 of a reference voltage source 28 in a comparing amplifier 27, and a level higher than the voltage 30 is detected. Consequently, a synchronizing signal 31 which has the phase delayed somewhat but has no erroneous output is obtained from the amplifier 27. This synchronizing signal 31 is supplied to a delay pulse generator 18, and the generator 18 generates pulses 20 only in the back porch time, and a normal signal to be detected is obtained. That is, even if an erroneous synchronizing signal is outputted once to lock an AGC erroneously, a normal AGC operation is performed.
摘要翻译：目的：通过在同步信号分离电路和延迟脉冲发生器之间设置LPF和比较放大器，当从分离电路产生的同步信号的脉冲宽度窄于规定值时，难以产生故障。构成：从同步信号分离电路10产生的同步信号11通过LPF26成为信号29。将该信号29与比较放大器27中的参考电压源28的电压30进行比较，并且检测到高于电压30的电平。因此，从放大器27获得具有稍微延迟但没有错误输出的相位的同步信号31.该同步信号31被提供给延迟脉冲发生器18，并且发生器18仅在后沿时间产生脉冲20 ，并且获得要检测的正常信号。也就是说，即使输出错误的同步信号一次来错误地锁定AGC，就执行正常的AGC操作。

92. 发明专利

JPS58210721A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS58210721A
公开(公告)日：1983-12-08
申请号：JP9311182
申请日：1982-06-02
申请人： Hitachi Ltd
发明人： FURUHATA MAKOTO
IPC分类号： H03K19/091
CPC分类号： H03K19/091
摘要： PURPOSE:To make the injector currents of I L circuits of multistage (stacked) constitution constant, by using the 1st I L circuit and the 2nd I L circuit connected in series with the negative side current line of the 1st I L circuit. CONSTITUTION:Constant-current (injector) transistors TRQ11 and TRQ1n and switching TRs Q21 and Q2n constitute the 1st-stage I L circuit. Further, constant- current TRs Q11' and Q1n' and switching TRs Q21' and Q2n' constitute the 2nd- stage I L circuit. Those I L circuits are connected in series to form two-stage constitution. Namely, an injection current IO1 is supplied from a constant current source to the positive power supply line (emitter of pnp TR Q11 or Q1n) of the 1st-stage I L circuit. Further, the negative current source supply line (base of pnpTRQ11 or Q1n and emitter of npnTRQ21 or Q2n) of the 1st-stage I L circuit is connected to the positive power supply line (emitter of pnpTRQ11' or Q1n') of the 2nd I L circuit. Then, the I L circuit of the other stage is provided to the negative-side power supply line of the 1st-stage I L circuit and a dummy gate for switching current compensation is provided to the output gate.
摘要翻译：目的：通过使用与负侧电流线串联连接的第一I 2 L电路和第二I <2> L电路，使多级（堆叠）结构的I <2 L电路的注入电流恒定的第一个I <2> L电路。构成：恒流（注入）晶体管TRQ11和TRQ1n以及开关TRs Q21和Q2n构成第一级I <2> L电路。此外，恒流TRs Q11'和Q1n'以及开关TRs Q21'和Q2n'构成第二级I <2> L电路。这些I 2 L电路串联连接，形成两级结构。即，从恒流源向第一级I 2 L电路的正电源线（pnp TR Q11或Q1n的发射极）供给注入电流IO1。此外，第一级I 2 L电路的负电流源电源线（pnpTRQ11或Q1n的基极和npnTRQ21或Q2n的发射极）连接到正电源线（pnpTRQ11'或Q1n'的发射极）第二个I <2> L电路。然后，将另一级的I <2> L电路提供给第一级I <2> L电路的负侧电源线，并向输出门提供用于开关电流补偿的虚拟栅极。

93. 发明专利

JPS58202627A Electronic circuit 失效
标题翻译：电子电路
公开(公告)号：JPS58202627A
公开(公告)日：1983-11-25
申请号：JP8487582
申请日：1982-05-21
申请人： Hitachi Ltd
发明人： FURUHATA MAKOTO
IPC分类号： H03K19/091
CPC分类号： H03K19/091
摘要： PURPOSE:To reduce the chip area and to improve the product yield, by using an NPN transistor which functions as a constant current circuit to an injector current and furthermore applies bias voltage. CONSTITUTION:An output signal Vout is obtained through output terminals T4 and T3 in response to the polarity of an input signal Vin. In this case, injector currents of I L1 and I L2 flow to a transistor TRQ12 during the working of a circuit. Then the prescribed bias voltage is applied to a linear differential amplifier consisting of the I L1, I L2, a TRQ17 and a TRQ18 by the collector-emitter voltage of the TRQ12. This TRQ12 functions as a constant current circuit for the injector current and furthermore applies the bias voltage and consists of an NPN TR. This circuit reduces the chip area as well as the variation of the bias voltage due to the TRQ12. Thus the product yield is improved.
摘要翻译：目的：通过使用作为注入电流的恒流电路的NPN晶体管来减少芯片面积并提高产品产量，并施加偏置电压。构成：响应于输入信号Vin的极性，通过输出端子T4和T3获得输出信号Vout。在这种情况下，在电路工作期间，I 2 L1和I 2 L2的注入电流流向晶体管TRQ12。然后，通过TRQ12的集电极 - 发射极电压将规定的偏置电压施加到由I 2 L1，I 2 L2，TRQ 17和TRQ 18组成的线性差分放大器。该TRQ12用作喷射器电流的恒流电路，并且还施加偏置电压并由NPN TR组成。该电路减少了芯片面积以及由于TRQ12引起的偏置电压的变化。因此产品产量提高。

94. 发明专利

JPS5887905A CURRENT MIRROR CIRCUIT 失效
公开(公告)号：JPS5887905A
公开(公告)日：1983-05-25
申请号：JP18541981
申请日：1981-11-20
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO
IPC分类号： H03F3/34 , H03F3/343 , H03F3/347
摘要： PURPOSE:To obtain currents changed in an accurate rate, by providing a plurality of current mirror circuits in series and picking up an output from each current mirror circuit. CONSTITUTION:A current IO flows between the collector and emitter of a transistor (TR)Q11, and a base current IB1 is applied to TRsQ11, Q12. A current is supplied from the TRsQ11, Q12 to TRsQ13, Q14. Similarly, power is supplied to TRsQ17-Q24 from TRsQ13-Q16. An output current of a current mirror circuit consisting of the TRsQ13-Q16 is about 2IO, where IO is an output current of the current mirror circuit comprising the TRsQ11, Q12, and an output current of the current mirror circuit consisting of the TRsQ17-Q24 is about 4IO. The current ratio of each output current is taken as 1:2:4:8, allowing to obtain suitable current sources for a digital-analog converter.

95. 发明专利

JPS57155830A COMPARATOR 失效
公开(公告)号：JPS57155830A
公开(公告)日：1982-09-27
申请号：JP4031081
申请日：1981-03-23
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO
IPC分类号： H03K5/08 , H03K19/018
摘要： PURPOSE:To achieve direct driving of a TTL logical circuit with an output of a differential pair transistors (TRs), by connecting a constant current load to the collector of the differential pair TRs receiving an input signal. CONSTITUTION:A constant current load I0 flowing a 1/2 current of the constant current source 2I0 to the collector of differential pair transistors Q1 and Q2 to the emitter of which the constant current source 2I0 is connected, is provided. To the collectors of the TRs Q1 and Q2, an inverter circuit consisting of input TRs Q3 and Q6, output TRs Q4, Q5, Q7 and Q8, diodes D1, D2, D3 and D4, and a resistor is connected. When an input signal Vin is greater than a reference signal Vref, the TRQ1 turns on and the Q2 turns off and the load constant current at the Q1 side all passes through the TRQ1, then the input TRQ6 turns off and an output OUT attains high level.

96. 发明专利

JPS5737922A A/d converter and its output extending system 失效
标题翻译： A / D转换器及其输出扩展系统
公开(公告)号：JPS5737922A
公开(公告)日：1982-03-02
申请号：JP11023180
申请日：1980-08-13
申请人： Hitachi Ltd
发明人： FURUHATA MAKOTO
IPC分类号： H03M1/18 , H03M1/00 , H03M1/12 , H03M1/20 , H03K13/02
CPC分类号： H03M1/361
摘要： PURPOSE:To ensure an easy extension of the output bit, by adding a function that forcibly fix the digital output signal at a prescribed level by an underflow signal or a signal supplied from outside. CONSTITUTION:The analog signal supplied from a terminal A is compared with the reference voltage through a comparator 1. The output of the comparator 1 is converted into a digital signal of the gray code through an output circuit 2 and applied to a converting cirucit 4 via a master latching circuit 3 to be converted into a binary code. This converted binary code is taken into a slave latching output circuit 5. On the other hand, the underflow detecting signal detected at the comparator 1 is applied to a gate circuit 7 via an underflow master latching circuit 6. The circuit 7 carries out a control to or not to transmit the control signal given from a terminal L to a slave latching circuit 8 and at the same time fixes forcibly the output binary code of the circuit 4 at a prescribed level by the underflow signal.
摘要翻译：目的：为了确保输出位的简单扩展，通过添加一个功能，通过下溢信号或从外部提供的信号强制将数字输出信号固定在规定的水平。构成：通过比较器1将从端子A提供的模拟信号与参考电压进行比较。比较器1的输出通过输出电路2转换为灰度代码的数字信号，并通过输出电路2施加到转换电路4 主锁存电路3转换成二进制码。该转换的二进制码被送入从锁存输出电路5.另一方面，在比较器1处检测到的下溢检测信号通过下溢主锁存电路6被施加到门电路7.电路7执行控制是否将从端子L给出的控制信号发送到从锁存电路8，并且同时通过下溢信号强制地将电路4的输出二进制码固定在规定的电平。

97. 发明专利

JPS5622523A POWER SUPPLY VOLTAGE DROP DETECTOR CIRCUIT 失效
公开(公告)号：JPS5622523A
公开(公告)日：1981-03-03
申请号：JP9729979
申请日：1979-08-01
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO
IPC分类号： H02H3/24

98. 发明专利

JPS55140330A CURRENT DIVISION UNIT 失效
公开(公告)号：JPS55140330A
公开(公告)日：1980-11-01
申请号：JP4795279
申请日：1979-04-20
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO , TAKAHASHI KIYOUICHI
IPC分类号： H03K19/091
摘要： PURPOSE:To obtain a simplified current dividing circuit by providing plural emitters and collectors, where effective emitter and collector areas are set in respective division ratios, and a base biased commonly. CONSTITUTION:The effective emitter area ratio of P-type semiconductor regions 1a and 1b which constitute the injector of an I L circuit is set to, for example, 1:2, and effective collector areas of P-type semiconductor regions 2a1-2a3 and 2b1-2b4 which constitute collectors corresponding to them are divided into three and four equally respectively. N type semiconductor region 3 constitutes a practical base region and is biased to the earth potential. If emitter regions 1a and 1b are made common and constant current I0 is flowed, the current input from injector 1a to collectors 2a1-2a3 becomes I0/3X1/3=10/9. Meanwhile, the current input from injector 1b to collectors 2b1-2b4 becomes 2I0/3X1/4=I0/6. Consequently, different constant current loads can be obtained from one constant current source by a simplified circuit.

99. 发明专利

JPS55130206A WAVEFORM CONVERSION CIRCUIT AND FM MODULATOR USING CIRCUIT THEREOF 失效
公开(公告)号：JPS55130206A
公开(公告)日：1980-10-08
申请号：JP3686279
申请日：1979-03-30
申请人： HITACHI LTD
发明人： KASHIMA HIDEO , FURUHATA MAKOTO
IPC分类号： H03D3/00 , H03D3/04
摘要： PURPOSE:To obtain a waveform conversion circuit featuring the steady operation by excluding the capacitor which is hard to be formed as the semiconductor element within the semiconductor integrated circuit. CONSTITUTION:The intermediate-frequency signal sent from intermediate-frequency filter 24 is applied to terminal 1' and then converted into the rectangular wave signal featuring the complementary relation through amplitude limiter 1 to be amplified by differential amplifier 2. The trapezoid wave signal is produced via charging circuit 3a, discharging circuit 3b and capacitor C2 and with use of the amplified signal of one side. In the same way, the rectangular wave signal is produced through waveform shaping circuit 4. These two signals receive the regulation of the amplitude level through constant voltage circuit 5 plus 1st and 2nd voltage limit circuits 6 and 7 each. After this, the two trapezoid wave signals of different amplitude levels are produced from the trapezoid wave signal through 1st level shift circuit 9. In the same way, the two rectangular wave signals of different amplitude levels are produced in the same way through 2nd level shift circuit 10. These trapezoid and rectangular wave signals are supplied to voltage comparator circuit 11, and thus the pulse signal of the fixed duration is produced at the zero-level crossing position of the intermediate-frequency signal.

100. 发明专利

JPS5448458A PROGRAMMABLE DIVIDER 失效
公开(公告)号：JPS5448458A
公开(公告)日：1979-04-17
申请号：JP11459877
申请日：1977-09-26
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO
IPC分类号： H03K23/66 , G06F1/04
摘要： PURPOSE:To enable the divider operationable at high frequency band and to reduce the chip size, by taking the signal based on the logical product output of each frequency dividing stage output as the reset signal for the second frequency divider, and by taking the signal based on the logical product output of the reset signal of each frequency dividing output and the second frequency divider as the reset signal for the first frequency divider. CONSTITUTION:At least, the divider has the first frequency divider 1 constituted with the high speed logic circuit and the second frequenct divider 2 constitutd with low speed logic circuit, and the output of the first frequency divider 1 is taken as the input of the second frequency divider 2. The first frequency divider Z takes the signal based on the logical product output of each frequency dividing output as the reset signal, and in the first frequency divider 1, by resetting the signal based on the reset signal based on the logical product output of each frequency dividing output and the second frequency divider 2, it is operationalbe at high frequency band and the chip size can be reduced.

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