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1. 发明专利

JPH0816474A MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH0816474A
公开(公告)日：1996-01-19
申请号：JP14735494
申请日：1994-06-29
申请人： HITACHI LTD
发明人： MORIOKA MICHIO , KUROSAWA KENICHI , NAKAMIGAWA TETSUAKI , ISHIKAWA SUKETAKA
IPC分类号： G06F15/16 , G06F12/08 , G06F15/163 , G06F15/177
摘要： PURPOSE:To guarantee matching at a high speed by storing data information which is registered in other clusters among data in the local memory of own cluster and deciding a range wherein cache memory contents should be matched. CONSTITUTION:A cluster 100 is constituted by connecting plural processors 200 equipped with cache memories 250, a cluster communication controller 500 equipped with an export directory 600, and a local memory 400 to a processor memory interface device 300. Then plural clusters 100 are connected to a cluster bus 2200 through the cluster communication controller 500 to form large-scale multiprocessor constitution on the whole. When data in the local memory in own cluster 100 are registered in the cache memory 250 of another cluster, the address of the data is registered in the export directory 600 and on the basis of the storage contents, the range wherein the contents of the cache memory 250 are matched is decided.

2. 发明专利

JPH0317132B2 失效
公开(公告)号：JPH0317132B2
公开(公告)日：1991-03-07
申请号：JP24549083
申请日：1983-12-28
申请人： HITACHI LTD
发明人： SAKAI TATSUYA , ISHIKAWA SUKETAKA
IPC分类号： G06F7/537 , G06F7/508 , G06F7/52 , G06F7/535

3. 发明专利

JPH0234054B2 失效
公开(公告)号：JPH0234054B2
公开(公告)日：1990-08-01
申请号：JP11955683
申请日：1983-07-01
申请人： HITACHI LTD
发明人： OOTSUKI TOORU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , YABE HIDEAKI , FUKUDA MASAHARU
IPC分类号： G06F7/496 , G06F7/491 , G06F7/506 , G06F7/508 , G06F7/52 , G06F7/527

4. 发明专利

JPS63289644A MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS63289644A
公开(公告)日：1988-11-28
申请号：JP12475087
申请日：1987-05-21
申请人： HITACHI LTD
发明人： ISHIKAWA SUKETAKA , SAWADA SHIGEO
IPC分类号： G06F9/28 , G06F9/22
摘要： PURPOSE:To shorten the required time of prescribed processing without increasing bit width unnecessarily by converting a part of a microsubinstruction into a subcode for specifying the items of composite operation in accordance with the value of a control code area. CONSTITUTION:When the value of the control code area 2 in the microinstruction 1 read out from a control memory is '11', a composite operation subcode 5 is transmitted to control parts for plural computing elements such as an 1-byte adder BA, an 8-byte adder PA and an 8-byte shifter SH and registers R1-R4. Each control part forms a control signal from the code 5 and finds out OR operation between the formed control signal and a control signal required for independent operation of each element out of respective computing elements and registers R1-R4. Consequently, respective computing elements and respective registers R1-R4 are controlled and the various operations of these elements are uniformly determined by one value of the code 5.

5. 发明专利

JPS58140846A DIVIDING SYSTEM OF BINARY CODED DECIMAL 失效
公开(公告)号：JPS58140846A
公开(公告)日：1983-08-20
申请号：JP2323082
申请日：1982-02-16
申请人： HITACHI LTD
发明人： OOTSUKI TOORU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , FUKUDA MASAHARU
IPC分类号： G06F7/491 , G06F7/493 , G06F7/496 , G06F7/508 , G06F7/52
摘要： PURPOSE:To reduce the absolute value of the address of a quotient estimating table and to save the quantity of data for a dividing system of binary coded decimal using the quotient estimating table, by modifying the redundant part in a bit supplied to a decoder. CONSTITUTION:When the quotient of binary coded decimal is obtained by one digit, the upper 3 bits of a divided register 1 and the upper 2 bits of a divisor register 3 are fed to a table address decoder 9. These total 5 bits are decoded to an address of 4 bits. Thus 1 bit is reduced, and other 4 bits are decoded as they are. Then the address region of a quotient estimating table 4 is enlarged to a double entry by means of the last one bit.

6. 发明专利

JPS58140845A DECIMAL ARITHMETIC SYSTEM 失效
公开(公告)号：JPS58140845A
公开(公告)日：1983-08-20
申请号：JP2323182
申请日：1982-02-16
申请人： HITACHI LTD
发明人： FUKUDA MASAHARU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , OOTSUKI TOORU
IPC分类号： G06F7/494 , G06F7/50 , G06F7/507 , G06F7/508
摘要： PURPOSE:To eliminate the recompensation after an operation and therefore to shorten the arithmetic processing time, by always obtaining a binary coded decimal in the form of absolute value through the same cycle operation regardless of the fact that the decimal operation is substantially an addition or a subtraction. CONSTITUTION:An addition or subtraction is carried out between two binary coded decimals to obtain an arithmetic result of binary coded decimal. In this system, the arithmetic result output of an adder 4 is selected in case an output having no compensation is delivered from the 1st deciding circuit 6 that decides whether a complement of arithmetic result is obtained or not. Then the output of the 2nd deciding circuit 5 feeds the arithmetic result output as it is to the digit having a carry in an arithmetic mode. The arithmetic result output is added with the compensating value before it is fed to the digit having no carry. When an output having compensation is delivered from the circuit 6, the complement output of (1) is selected for the arithmetic result of the adder 4. This complement of (1) is added with the compensating value before it is delivered to the digit having a carry. While the complement of (1) is delivered as it is to the digit having no carry.

7. 发明专利

JPS5794972A INFORMATION PROCESSOR 失效
公开(公告)号：JPS5794972A
公开(公告)日：1982-06-12
申请号：JP16960880
申请日：1980-12-03
申请人： HITACHI LTD
发明人： YABE HIDEAKI , ISHIKAWA SUKETAKA
IPC分类号： G06F12/16 , G06F11/00 , G06F12/08
摘要： PURPOSE:To continue processing without using a buffer storage BS even if the contents of an address register has an error, by sending a coincidence signal only when the contents of the address buffer and those of a buffer address array BAA are coincident with each other. CONSTITUTION:When an error detector 14 detects an error, a comparator 15 supplies a dissidence signal to an AND gate 17 through a line 15b without reference to coincidence between the high-order address bits of an address register 11 and a BAA 12. Then, data from a BS13 is not used and the address of the register 11 is supplied to an MS to output the readout data of the MS through the gate 17 and an OR gate 18. The dissidence signal opens AND gates 19 and 20 to store new data from the MS and its corresponding address in the BS13 and BAA12. Thus, processing is continued by using the data in the MS without using the BS13.

8. 发明专利

JPS55105900A ERROR CORRECTION*DETECTION SYSTEM 失效
公开(公告)号：JPS55105900A
公开(公告)日：1980-08-13
申请号：JP1227579
申请日：1979-02-07
申请人： HITACHI LTD
发明人： ISHIKAWA SUKETAKA , WATANABE YUTAKA , WAKAI KATSUROU
IPC分类号： G06F11/10 , G06F11/14 , G06F12/16
摘要： PURPOSE:To ensure the accurate detection for the state of error by giving the correction and the polarity inversion to the 1-bit error, if detected, and then having a comparison between the data which generated the redundant bit and the preceding data which gave the polarity inversion. CONSTITUTION:The data supplied to SEC-DED code generation circuit 2 is supplied to data register 11 after the polarity inversion given through polarity inverter 9 in case the 1-bit error is detected by SEC-DED circuit 6 and via the redundant bit added by circuit 2. This data is furthermore supplied to circuit 2 in the form of retrial writing data 12. Circuit 2 adds again the redundant bit corresponding to the data for writing. And this output 3 is written into memory device 4 and then read out. This reading code 5 receives the detection of the 1-bit error through circuit 6. After this, reading data 7 is supplied to comparator 23 to be compared with data 12. When the coincidence is obtained through the comparison, only 1-bit error exists. While in case no coincidence is obtained, the correction is given to the 3-bit error. And the correction of the error is informed to outside.

9. 发明专利

JPH0680487B2 失效
公开(公告)号：JPH0680487B2
公开(公告)日：1994-10-12
申请号：JP16931884
申请日：1984-08-15
申请人： HITACHI LTD
发明人： SAKAI TATSUYA , ISHIKAWA SUKETAKA
IPC分类号： G06F7/38 , G06F7/00 , G06F7/483 , G06F7/491 , G06F7/493 , G06F7/494 , G06F7/50 , G06F7/76

10. 发明专利

JPH0578049B2 失效
公开(公告)号：JPH0578049B2
公开(公告)日：1993-10-28
申请号：JP2753183
申请日：1983-02-23
申请人： HITACHI LTD
发明人： OOTSUKI TOORU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , YABE HIDEAKI , FUKUDA MASAHARU
IPC分类号： G06F7/487 , G06F5/01 , G06F7/507 , G06F7/508 , G06F7/527 , G06F7/52 , G06F7/00

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