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1. 发明专利

JP2004289023A Inspecting method and apparatus for silicon carbide semiconductor device, and manufacturing method for silicon carbide semiconductor device 有权
公开(公告)号：JP2004289023A
公开(公告)日：2004-10-14
申请号：JP2003081539
申请日：2003-03-24
申请人： Central Res Inst Of Electric Power Ind , Fuji Electric Advanced Technology Co Ltd , 富士電機アドバンストテクノロジー株式会社 , 財団法人電力中央研究所
发明人： TAWARA TAKESHI , IZUMI SHUNSUKE , TSUCHIDA SHUICHI , KAMATA ISAO
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To inspect in a short time whether or not a lamination fault of a semiconductor device comprising a silicon carbide semiconductor or to manufacture the silicon carbide semiconductor device in a short time including its inspection time.
SOLUTION: An SiC wafer 9 having a pn junction comprising a p type silicon carbide semiconductor and an n type silicon carbide semiconductor is irradiated with laser light 2 having larger energy than a band gap of the silicon carbide semiconductor. Light 6 emitted from the SiC wafer 9 by the laser irradiation is analyzed with the aid of a spectroscope 4, and the intensity of a specific wavelength light is observed with a photomultiplier tube 5. The deterioration of the characteristics of the semiconductor device comprising the pn junction is determined on the basis of measured light intensity.
COPYRIGHT: (C)2005,JPO&NCIPI

2. 发明专利

JP2007165604A Silicon carbide bipolar semiconductor device 有权
标题翻译：碳化硅双极半导体器件
公开(公告)号：JP2007165604A
公开(公告)日：2007-06-28
申请号：JP2005360245
申请日：2005-12-14
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： ISHII RYUSUKE , NAKAYAMA KOJI , SUGAWARA YOSHITAKA , MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , NAKAMURA TOMONOBU
IPC分类号： H01L29/861 , H01L21/28 , H01L29/417
CPC分类号： H01L29/1604 , H01L21/0465 , H01L21/047 , H01L29/0615 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/8613
摘要： PROBLEM TO BE SOLVED: To suppress the generation of lamination defects and the area extension thereof in an SiC bipolar semiconductor device having a mesa-type shape, and obtained by growing epitaxially a first-conductivity SiC drift layer and a second-conductivity SiC charge injecting layer on the surface of an SiC single-crystal substrate, to suppress thereby the increase of its forward voltage, and further, to improve its withstanding voltage performance generated when applying a reversed voltage to it.
SOLUTION: On mesa walls or on both mesa walls and mesa peripheries of the SiC bipolar semiconductor device, there are formed degradation preventing layers due to conduction for separating spatially from each other the surfaces of both the mesa walls and mesa peripheral portions and its pn-junction interface. In an aspect, the degradation preventing layers due to conduction comprise second-conductivity silicon carbide low-resistance layers which are brought into equipotential layers when applying a reversed voltage to it. In another aspect, the degradation preventing layers due to conduction comprise second-conductivity silicon carbide conductive layers having metal films formed on their surfaces which are brought into equipotential films when applying a reversed voltage to it. In further another aspect, the degradation preventing layers due to conduction comprise high-resistance amorphous layers.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了抑制在具有台面形状的SiC双极型半导体器件中产生层叠缺陷及其面积扩大，并且通过外延生长第一导电性SiC漂移层和第二导电性 SiC电荷注入层，从而抑制其正向电压的增加，并且进一步提高对其施加反向电压时产生的耐受电压性能。解决方案：在SiC双极半导体器件的台面壁或台面壁和台面周边上，形成由于导电而导致的防锈层，以便在台面壁和台面周边部分的两个表面之间空间分离，其pn结界面。一方面，由于导电而导致的防止降解层包括第二导电性碳化硅低电阻层，当向其施加反向电压时，其被引入等电位层。另一方面，由于导电而导致的防止降解层包括在其表面上形成有金属膜的第二导电性碳化硅导电层，当向其施加反向电压时，其被引入等电位膜。在另一方面，由于传导而导致的防止降解层包括高电阻非晶层。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007027630A Bipolar semiconductor device and its manufacturing method 审中-公开
标题翻译：双极半导体器件及其制造方法
公开(公告)号：JP2007027630A
公开(公告)日：2007-02-01
申请号：JP2005211296
申请日：2005-07-21
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , SUGAWARA YOSHITAKA , NAKAYAMA KOJI , ISHII RYUSUKE
IPC分类号： H01L29/861 , H01L21/336 , H01L29/161 , H01L29/739 , H01L29/74 , H01L29/744 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To suppress generation of lamination defects and the enlargement of area of lamination defect which are generated by continuing the supply of electric power, in a silicon carbide bipolar semiconductor device.
SOLUTION: A surface layer 4, at least high in seed defect density, is removed in a first conductive silicon carbide epitaxial film 2 grown from the front surface of the first conductive silicon carbide single crystal substrate 1 by chemical vapor deposition method, and thereafter, a second conductive silicon carbide epitaxial film 3 is made to grow from the front surface of the silicon carbide epitaxial film 2, whose surface layer 4 is removed. Furthermore, after the second conductive silicon carbide epitaxial film 3 is grown, a surface layer 6 high at least in the seed defect density is removed in the second conductive silicon carbide epitaxial film 3.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：在碳化硅双极型半导体器件中，抑制通过继续供电而产生的层叠缺陷的产生和叠层缺陷的面积的扩大。解决方案：通过化学气相沉积法从第一导电碳化硅单晶衬底1的表面生长的第一导电碳化硅外延膜2中去除至少具有至少高的种子缺陷密度的表面层4，之后，使第二导电性碳化硅外延膜3从除去表面层4的碳化硅外延膜2的前表面生长。此外，在第二导电碳化硅外延膜3生长之后，在第二导电碳化硅外延膜3中除去至少晶种缺陷密度高的表面层6。（C）2007，JPO＆INPIT

4. 发明专利

JP2006237125A Method of operating bipolar type semiconductor device, and bipolar type semiconductor device 审中-公开
标题翻译：双极型半导体器件的操作方法和双极型半导体器件
公开(公告)号：JP2006237125A
公开(公告)日：2006-09-07
申请号：JP2005046850
申请日：2005-02-23
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： SUGAWARA YOSHITAKA , NAKAYAMA KOJI , ISHII RYUSUKE , MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO
IPC分类号： H01L29/861 , H01L21/329
摘要： PROBLEM TO BE SOLVED: To suppress the increase of a created stacking fault area by continuing energizing in a bipolar type semiconductor device which performs electron and hole recombination in the time of energization inside a silicon carbide epitaxial film grown up from the front surface of a silicon carbide single crystal substrate.
SOLUTION: A conducting operation is performed while the above SiC bipolar type semiconductor device is maintained in a temperature environment at 350°C or more.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了通过在从前表面生长的碳化硅外延膜内的通电时进行电子和空穴复合的双极型半导体器件中继续通电来抑制产生的堆垛层错区域的增加的碳化硅单晶基板。解决方案：在上述SiC双极型半导体器件保持在350℃以上的温度环境下进行导通操作。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2007318030A Crystal defect inspection method and crystal defect inspection apparatus of silicon carbide single crystal 有权
标题翻译：晶体缺陷检测方法和晶体缺陷检测装置的碳化硅单晶
公开(公告)号：JP2007318030A
公开(公告)日：2007-12-06
申请号：JP2006148565
申请日：2006-05-29
申请人： Central Res Inst Of Electric Power Ind , 財団法人電力中央研究所
发明人： TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , LIUTAURAS STORASTA
IPC分类号： H01L21/66 , G01N21/66
摘要： PROBLEM TO BE SOLVED: To provide a crystal defect inspection method and a crystal defect inspection apparatus capable of performing inspection quickly and inexpensively when inspecting the in-plane distribution of dislocation and lamination defects existing in the epitaxial film of a silicon carbide single-crystal wafer for manufacturing a semiconductor element by an electroluminescence method.
SOLUTION: Voltage is applied at an area to the back of a wafer, where the wafer is grounded by pushing out a liquid metal onto the epitaxial film at a measurement position from the tip of a tubular member, or bringing a conductive film electrode that is made to contact and separate from the wafer into contact. Then, the two-dimensional information of EL light from each position corresponding to an array at a collective measurement region in a wafer surface is acquired collectively by the two-dimensional CCD array from the back side of the wafer. Each collective measurement region in the wafer surface is scanned, thus obtaining mapping data related to the EL light in the entire region to be inspected in the wafer surface and specifying the positions of crystal defects in the wafer surface based on the data.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在检查存在于碳化硅单体的外延膜中的位错和层叠缺陷的面内分布时能够快速且廉价地进行检查的晶体缺陷检查方法和晶体缺陷检查装置用于通过电致发光法制造半导体元件的晶体晶片。解决方案：在晶片背面的一个区域上施加电压，其中通过在管状构件的尖端处的测量位置处将液态金属推出到外延膜上而将晶片接地，或者使导电膜使与晶片接触和分离的电极接触。然后，从晶片的背面通过二维CCD阵列一起获取与晶片表面的集体测量区域中的阵列对应的每个位置的EL光的二维信息。对晶片表面中的每个集体测量区域进行扫描，从而在晶片表面中获得要检查的整个区域中的EL光的映射数据，并基于该数据指定晶片缺陷的位置。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2009044083A Method of detecting defects of silicon carbide single crystal wafer and method of manufacturing silicon carbide semiconductor device 有权
标题翻译：检测碳化硅单晶的缺陷的方法及制造硅碳化硅半导体器件的方法
公开(公告)号：JP2009044083A
公开(公告)日：2009-02-26
申请号：JP2007210008
申请日：2007-08-10
申请人： Central Res Inst Of Electric Power Ind , 財団法人電力中央研究所
发明人： TSUCHIDA SHUICHI , KAMATA ISAO , NAGANO MASAHIRO
IPC分类号： H01L21/66 , G01N23/207
摘要： PROBLEM TO BE SOLVED: To specify a position and type of a specific basal-plane defect in a wafer surface nondestructively by discriminating the basal-plane defect from other dislocations and stacking faults when it is intended to manufacture a silicon carbide semiconductor device from a silicon carbide single crystal wafer, and what is more, to manufacture, based on the specified result, a silicon carbide semiconductor device having device characteristics which are free of any influence coming from the crystal defects.
SOLUTION: The method of detecting defects of silicon carbide single crystal wafer is characterized by: making a reflection X-ray topographic measurement in a wafer surface of a silicon carbide single crystal wafer; detecting a specific basal-plane defect nondestructively by identifying a specific diffraction pattern on the basis of the X-ray diffraction data in the wafer surface obtained by the reflection X-ray topographic measurement; and acquiring positional information of the detected basal-plane defect in the wafer surface. In addition, the method of manufacturing silicon carbide semiconductor device is set up using the method of detecting defects.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在制造碳化硅半导体器件时识别基底缺陷与其他位错和堆垛层错来指定晶片表面中特定基面缺陷的位置和类型从碳化硅单晶晶片，并且更具体地，基于指定的结果制造具有不受来自晶体缺陷的任何影响的器件特性的碳化硅半导体器件。检测碳化硅单晶晶片的缺陷的方法的特征在于：在碳化硅单晶晶片的晶片表面进行反射X射线形貌测量; 通过基于通过反射X射线形貌测量获得的晶片表面中的X射线衍射数据识别特定的衍射图案，非破坏性地检测特定的基底面缺陷; 并且获取晶片表面中检测到的基底缺陷的位置信息。此外，使用检测缺陷的方法来建立制造碳化硅半导体器件的方法。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2007318031A Manufacturing method of silicon carbide semiconductor element 有权
标题翻译：碳化硅半导体元件的制造方法
公开(公告)号：JP2007318031A
公开(公告)日：2007-12-06
申请号：JP2006148566
申请日：2006-05-29
申请人： Central Res Inst Of Electric Power Ind , 財団法人電力中央研究所
发明人： TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , LIUTAURAS STORASTA
IPC分类号： H01L21/66 , H01L21/336 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To manufacture a silicon carbide semiconductor element without any influence to element characteristics due to crystal defects by specifying the positions of dislocation and lamination defects in a wafer surface, and their types.
SOLUTION: The positions of the dislocation and lamination defects in the wafer surface, and their types are acquired from emission mapping data obtained by scanning the inside of the wafer surface for each collective measurement region in which luminous images are detected collectively by a two-dimensional CCD array. Based on the information, the semiconductor element after cutting/separation from the wafer is screened. In another embodiment, the formation position of each semiconductor element in the wafer surface is determined based on the information so that dislocation and lamination defects are avoided. Further, in another embodiment, processing for adding a structure is performed, where the structure is used to inactivate a part where the lamination defects are present to reduce influence to the element characteristics of the part.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过指定晶片表面中的位错和层叠缺陷的位置以及它们的类型，制造碳化硅半导体元件而不会由于晶体缺陷而对元件特性没有任何影响。解决方案：晶片表面中的位错和层叠缺陷的位置及其类型是从通过扫描由晶片表面的内部获得的每个集合测量区域获得的发射映射数据获取的，其中发光图像被集体检测二维CCD阵列。基于该信息，对从晶片进行切割/分离后的半导体元件进行筛选。在另一个实施例中，基于该信息确定晶片表面中的每个半导体元件的形成位置，从而避免位错和层叠缺陷。此外，在另一个实施例中，进行用于添加结构的处理，其中使用结构来使存在层叠缺陷的部分失活以减少对部件的元件特性的影响。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007269627A METHOD FOR MANUFACTURING SIC CRYSTAL TO REDUCE MICROPIPE PROPAGATING FROM SUBSTRATE AND SiC CRYSTAL, SiC SINGLE CRYSTAL FILM, SiC SEMICONDUCTOR ELEMENT, SiC SINGLE CRYSTAL SUBSTRATE AND ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SiC BULK CRYSTAL 审中-公开
标题翻译：用于制造SIC晶体以减少从基板和SiC晶体，SiC单晶体膜，SiC半导体元件，SiC单晶衬底和电子器件传播的微孔的方法及其制造SiC体积晶体的方法
公开(公告)号：JP2007269627A
公开(公告)日：2007-10-18
申请号：JP2007154121
申请日：2007-06-11
申请人： Central Res Inst Of Electric Power Ind , 財団法人電力中央研究所
发明人： KAMATA ISAO , TSUCHIDA SHUICHI
IPC分类号： C30B29/36 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a SiC crystal in which hollow-core defects that have propagated from a substrate can be reduced even when a SiC single crystal substrate having hollow-core defects called as micropipes is used. SOLUTION: A source gas having a C/Si atom number ratio adjusted to a range in which the crystal growth rate is determined by the carbon atom supply limitation is brought into contact with a SiC substrate; and a plurality of SiC crystal layers are epitaxially grown into layers to dissociate the hollow-core defects in the SiC single crystal substrate into dislocations given by small Burgers vectors in order to prevent the defects from propagating to the crystal surface. A first SiC crystal is formed as a buffer layer, and further a SiC crystal is layered thereon by using a source gas having a C/Si ratio adjusted to be higher than that when forming the buffer layer. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种SiC晶体，其中即使使用具有称为微管的中空芯缺陷的SiC单晶衬底，其也可以降低从衬底传播的空心缺陷。解决方案：将具有C / Si原子数比的调整到通过碳原子供应限制确定晶体生长速率的范围的源气体与SiC衬底接触; 并且多个SiC晶体层外延生长成层，以将SiC单晶衬底中的中空缺陷解离成由小汉堡矢量给出的位错，以防止缺陷传播到晶体表面。形成第一SiC晶体作为缓冲层，并且通过使用将C / Si比调节为高于形成缓冲层时的C / Si比的源气体，将SiC晶体层叠在其上。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2005167035A Silicon carbide semiconductor device and manufacturing method thereof 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2005167035A
公开(公告)日：2005-06-23
申请号：JP2003405259
申请日：2003-12-03
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： NAKAYAMA KOJI , SUGAWARA YOSHITAKA , ASANO KATSUNORI , TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , NAKAMURA TOMONOBU
IPC分类号： H01L21/331 , H01L21/04 , H01L21/329 , H01L21/336 , H01L29/04 , H01L29/12 , H01L29/24 , H01L29/73 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To prevent the increase of a forward voltage due to aging of a bipolar semiconductor device using a silicon carbide semiconductor.
SOLUTION: The plane having an off-angle θ as 8° with respect to the (000-1) carbon plane of a silicon carbide semiconductor crystal is made to be a growth plane of crystal. A buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on this growth plane with an increase speed of the film thickness per hour (h) which is not less than 3 times larger than that in the prior art, i.e. with film formation speed of 10 μm/h. The flow rate of the raw material gases, which are silane, propane, and a dopant gas are greatly increased to increase the film formation speed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由于使用碳化硅半导体的双极性半导体器件的老化引起的正向电压的增加。解决方案：将具有相对于碳化硅半导体晶体的（000-1）碳平面的偏角θ为8°的平面制成晶体的生长平面。在该生长平面上形成缓冲层，漂移层和其他p型和n型半导体层，每小时（h）的膜厚度的增加速度不小于先前的3倍即成膜速度为10μm/ h。作为硅烷，丙烷和掺杂剂气体的原料气体的流量大大增加以提高成膜速度。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2009088547A Method and device for inspecting silicon carbide semiconductor device, and method for manufacturing the silicon carbide semiconductor device 有权
标题翻译：用于检查碳化硅半导体器件的方法和装置以及用于制造碳化硅半导体器件的方法
公开(公告)号：JP2009088547A
公开(公告)日：2009-04-23
申请号：JP2008305880
申请日：2008-12-01
申请人： Central Res Inst Of Electric Power Ind , 財団法人電力中央研究所
发明人： TAWARA TAKESHI , IZUMI SHUNSUKE , TSUCHIDA SHUICHI , KAMATA ISAO
IPC分类号： H01L21/66 , G01N21/956
摘要： PROBLEM TO BE SOLVED: To provide a method for inspecting whether there are defects in the lamination of a semiconductor device, constituted of silicon carbide semiconductor, in a short time.
SOLUTION: A semiconductor wafer (SiC wafer) 9 is irradiated with a laser beam 2, having bigger energy than that of a band gap of the silicon carbide semiconductor. The light 6 which is irradiated from the semiconductor wafer with the laser irradiation is dispersed by a wavelength selecting means (spectroscope) 4 to observe the intensity of the light, with a specific wavelength with a measuring means (photomultiplier tube) 5. Deterioration in the characteristics of the semiconductor device is determined, based on the light intensity measured.
COPYRIGHT: (C)2009,JPO&INPIT

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