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1. 发明公开

EP4364145A1 LOW-LEAKAGE DRAIN-PROGRAMMED ROM 审中-实审
公开(公告)号：EP4364145A1
公开(公告)日：2024-05-08
申请号：EP22741930.6
申请日：2022-06-17
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Xiao , HSIEH, Chen-Ju , SON, Sung , JUNG, Chulmin
IPC分类号： G11C17/12 , H10B69/00
CPC分类号： G11C17/126 , H10B20/34

2. 发明授权

EP3121818B1 METHOD TO PROGRAM BITCELLS OF A ROM ARRAY 有权
公开(公告)号：EP3121818B1
公开(公告)日：2018-08-22
申请号：EP15178040.0
申请日：2015-07-23
申请人： Synopsys, Inc.
发明人： Rawat, Anil Singh , Singh, Pritender
IPC分类号： G11C17/10 , G11C17/12 , G11C17/18 , G06F17/50 , H01L27/112
CPC分类号： G11C17/12 , G06F17/5045 , G11C17/10 , G11C17/123 , G11C17/126 , G11C17/18 , H01L27/11213
摘要： A method to program bitcells (11, ..., mn) of a ROM array (10) uses different programming cells (0a, ..., 0h, 1a, ..., 1d) for programming the bitcells (11, ..., mn) with a first or second data item. A first bitcell (11) is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance. All other bitcells (12, 13) located in the same column (C1) as the first bitcell (11) and subsequent rows (R2, R3) are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column (C1).

3. 发明公开

EP2823486A1 VOLTAGE MODE SENSING FOR LOW POWER FLASH MEMORY 有权
标题翻译：电压模式集合低功耗闪存
公开(公告)号：EP2823486A1
公开(公告)日：2015-01-14
申请号：EP13708636.9
申请日：2013-03-01
申请人： Medtronic Inc.
发明人： WALSH, Kevin K. , PATTERSON, Paul B. , BENTON, Glen W. , WILKINSON, Jeffrey D.
IPC分类号： G11C16/28 , G11C16/26 , G11C7/08 , G11C7/22 , G11C7/14 , G11C11/00 , G11C17/12 , G11C29/50
CPC分类号： G11C16/30 , G11C7/065 , G11C7/08 , G11C7/14 , G11C7/227 , G11C11/005 , G11C16/26 , G11C16/28 , G11C17/12 , G11C29/50 , G11C29/50004
摘要： Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.

4. 发明公开

EP1744324A1 Mémoire à lecture seule 审中-公开
标题翻译：努尔 - Lese酒店 - 斯派克
公开(公告)号：EP1744324A1
公开(公告)日：2007-01-17
申请号：EP06116679.9
申请日：2006-07-05
申请人： ST MICROELECTRONICS S.A.
发明人： Jacquet, François
IPC分类号： G11C17/12 , G11C7/18 , G11C11/4097 , H01L27/112
CPC分类号： H01L27/112 , G11C7/18 , G11C17/12
摘要： L'invention concerne une matrice de cellules d'une mémoire à lecture seule constituées chacune d'un transistor dont une première région (d) de drain ou de source est connectée à une ligne de bit (BL) reliant plusieurs transistors dans une première direction, les grilles (g) des différents transistors étant connectées à des lignes de mot (WL) dans une deuxième direction perpendiculaire à la première, la matrice comportant une répétition d'un motif élémentaire s'étendant sur trois lignes dans chaque direction et comportant neuf transistors disposés de façon que chacune des lignes du motif élémentaire comporte deux cellules, deux transistors voisins de chaque motif dans la première direction partageant une même deuxième région (s) reliée à une ligne de masse et étant reliés à des lignes de bit différentes d'une ligne de mot à l'autre.
摘要翻译：矩阵具有在每个方向上在三个位线上延伸的基本图案的重复，并且包括九个N沟道金属氧化物半导体（MOS）晶体管，其中一个晶体管的两个区域由接地导线互连。晶体管以这样的方式设置，使得每条线包括两个单元和两个N沟道MOS晶体管，其在与连接到不同于一个字线到另一个字线的位线的地线连接的相同区域的方向上在每个图案附近字线。对于具有单元矩阵的只读存储器还包括独立权利要求。

5. 发明公开

EP1443520A3 Semiconductor memory device 审中-公开
公开(公告)号：EP1443520A3
公开(公告)日：2006-07-19
申请号：EP04250463.9
申请日：2004-01-28
申请人： SHARP KABUSHIKI KAISHA
发明人： Morikawa, Yoshinao
IPC分类号： G11C16/04 , G11C16/26 , G11C17/12
CPC分类号： G11C17/126 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0064 , G11C16/0475 , G11C16/0491 , G11C16/26 , G11C2213/31
摘要： The present invention prevents a reading operation margin from being decreased due to a current injected into a selected bit line after passing through an unselected bit line in a memory cell array configuration using virtual ground lines. A memory cell array (1) is constituted by being divided into at least subarrays (2) of a plurality of columns and memory cell columns at the both ends of the subarrays (2) are constituted so that second electrodes are not connected each other but they are separated from each other between two memory cells adjacent to each other in the row direction at the both sides of boundaries between the subarrays (2) and respectively connected to an independent bit line or virtual ground line, and one of word lines, one of bit lines, and one of virtual ground lines are selected and one memory cell from which data will be read is selected.

6. 发明授权

EP1434236B1 Semiconductor memory device generating accurate internal reference voltage 有权
标题翻译：与精确的内部基准电压产生的半导体存储器件
公开(公告)号：EP1434236B1
公开(公告)日：2005-12-28
申请号：EP04004987.6
申请日：2000-03-03
申请人： Oki Electric Industry Co. Ltd., Legal & Intellectual Property Division
发明人： Miyamoto, Kenichi Micro Design Co. LTD
IPC分类号： G11C17/12 , G11C7/14
CPC分类号： G11C17/126 , G11C7/14 , G11C17/123

7. 发明公开

EP0822558A3 High-speed low-power consumption semiconductor non-volatile memory device 失效
标题翻译：高的速度和低的消耗非易失性半导体存储器件
公开(公告)号：EP0822558A3
公开(公告)日：2003-07-30
申请号：EP97113033.1
申请日：1997-07-29
申请人： NEC Corporation , NEC Electronics Corporation
发明人： Hirano, Masanori, NEC IC Microcomp. Syst. Ltd.
IPC分类号： G11C17/12
CPC分类号： G11C17/123
摘要： A current source (55) of a semiconductor read only memory device supplies current through a digit line (DL0-DLk) to a memory cell so as to seen whether the memory cell is implemented by an enhancement type transistor or a depletion type transistor, and a potential transferring circuit (57) either discharges a precharge level from an input line (SIL) connected to a sense amplifier (52) or maintains the precharge level depending upon the potential level at the drain node of the memory cell so that a small amount of parasitic capacitance of the input line allows the sense amplifier to rapidly determine the operation mode of the memory cell.

8. 发明公开

EP1047079A3 Semiconductor memory device generating accurate internal reference voltage 有权
标题翻译： Halbleiterspeicheranordnung mit genauer interner Referenzspannungserzeugung
公开(公告)号：EP1047079A3
公开(公告)日：2002-07-10
申请号：EP00104670.5
申请日：2000-03-03
申请人： Oki Electric Industry Co., Ltd.
发明人： Miyamoto, Kenichi, c/o OKI Micro Design Co., Ltd.
IPC分类号： G11C17/12 , G11C7/14
CPC分类号： G11C17/126 , G11C7/14 , G11C17/123
摘要： A semiconductor memory device has a memory cell array that outputs cell current to data sensing amplifiers and reference current to reference amplifiers. The reference amplifiers convert the reference current to a reference voltage. The data sensing amplifiers use the reference voltage to convert the cell current to a data voltage signal. According to a first aspect of the invention, reference current is supplied to a reference amplifier from two parallel data paths, each having approximately equal numbers of transistors of two types, one type of which is always switched on, the other type switching on and off. According to a second aspect of the invention, each data sensing amplifier, and the reference amplifier to which it is connected, receive currents from parts of the memory cell array having identical layouts.
摘要翻译：存储单元阵列包括具有交替类型的晶体管（1,2）的两个并联电流路径（18,19）的数据单元列（10A）和参考单元列（17）。参考放大器（16）将参考电流（Iref）转换为参考电压（Vref）和从具有相同布局的阵列的部分接收电流的数据感测放大器（13）使用参考电流来转换单元电流（ Icell）到数据电压信号（Vs）。

9. 发明授权

EP0797214B1 Semiconductor storage device 失效
公开(公告)号：EP0797214B1
公开(公告)日：2001-11-28
申请号：EP96110756.2
申请日：1996-07-03
申请人： SHARP KABUSHIKI KAISHA
发明人： Suminaga, Yasuo , Komatsu, Koji
IPC分类号： G11C17/12 , G11C7/00
CPC分类号： G11C11/5692 , G11C7/18 , G11C17/126

10. 发明授权

EP0763830B1 Speicherzellenanordnung aus matrixförmig angeordneten Speicherzellen 失效
标题翻译：以矩阵形式布置的存储单元的存储单元阵列
公开(公告)号：EP0763830B1
公开(公告)日：2001-11-14
申请号：EP96114002.7
申请日：1996-08-30
申请人： Infineon Technologies AG
发明人： Von Basse, Paul-Werner , Thewes, Roland, Dr. , Schmitt-Landsiedel, Doris, Dr. , Bollu, Michael, Dr.
IPC分类号： G11C17/12
CPC分类号： G11C7/12 , G11C17/126

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