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1. 发明公开

EP1634296A4 NON-VOLATILE ELECTROMECHANICAL FIELD EFFECT DEVICES AND CIRCUITS USING SAME AND METHODS OF FORMING SAME 审中-公开
标题翻译：不挥发机电场效应模块和电路，以便及其制造方法
公开(公告)号：EP1634296A4
公开(公告)日：2007-02-14
申请号：EP04754836
申请日：2004-06-09
申请人： NANTERO INC
发明人： BERTIN CLAUDE L , RUECKES THOMAS , SEGAL BRENT M , VOGELI BERNHARD , BROCK DARREN K , JAIPRAKASH VENKATACHALAM C
IPC分类号： G11C23/00 , G11C7/06 , G11C8/02 , G11C11/00 , G11C11/50 , G11C13/02 , G11C16/02 , G11C16/04 , G11C17/16 , H01H59/00 , H01J1/62 , H01L20060101 , H01L21/336 , H01L21/82 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L27/28 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/76 , H01L51/00 , H01L51/05 , H01L51/30 , H03K17/16
CPC分类号： H01L29/78 , B82Y10/00 , B82Y99/00 , G11C7/065 , G11C13/025 , G11C16/0416 , G11C17/16 , G11C17/165 , G11C23/00 , G11C2213/16 , G11C2213/17 , G11C2213/79 , H01H1/0094 , H01L27/10 , H01L27/1052 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/286 , H01L29/0665 , H01L29/0673 , H01L29/42324 , H01L51/0048 , H01L51/0052 , H01L51/0508 , Y10S977/708 , Y10S977/724 , Y10S977/742 , Y10S977/762 , Y10S977/936 , Y10S977/938 , Y10S977/94 , Y10S977/943
摘要： Non-volatile field effect devices and circuits using same. A non-volatile field effect transistor utilizes a nanatube-based mechanical switch (30). The switch location can be at the source, drain or gate locations of the field effect transistor. Under one embodiment, the field effect device includes a source region and a drain region with a channel region (27) disposed therebetween. The source region is connected to a corresponding terminal (T2). A gate structure is disposed over the channel region and connected to a corresponding terminal (T1). A nanotube switching element (30) is responsive to a first control terminal (T3) and a second control terminal (T4) and is electrically positioned in series between the drain region and a terminal corresponding to the drain region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the drain region and its corresponding terminal.
摘要翻译：下一个方面，一种场效应器件包括栅极，源极和漏极，与该源极和漏极之间的导电通道; 和具有控制端子相对应的纳米管开关，所述纳米管开关被定位通过所述导电通道，以控制电传导。在另一个方面，场效应器件包括具有栅极端子相对应的栅极; 具有源极端子对应的A源; 具有漏极端子相对应的漏极; 一个控制端; 和纳米管的开关元件设置在栅极，源极中的一个，并且漏极和其相应的终端和切换之间，响应于在所述控制端的电刺激和栅极，源极中的至少一个，和漏极端子，第一非之间 -volatile状态没有启用源极和漏极以及第二非易失性状态之间的电流流动没有禁用源极和漏极之间的电流流动。

2. 发明公开

EP0166538A2 Two stage decoder circuit 失效
标题翻译： Zweistufige Decodierschaltung。
公开(公告)号：EP0166538A2
公开(公告)日：1986-01-02
申请号：EP85303790.1
申请日：1985-05-30
申请人： FUJITSU LIMITED
发明人： Okajima, Yoshinori
IPC分类号： G11C11/40 , H03M7/22 , G11C8/02
CPC分类号： G11C8/10 , H03M7/22
摘要： A two-state decoder circuit including a first-stage decoder circuit (7-1 to 8-2, 9, 10, 11), for decoding upper bits (Ao to A3) of an input signal, and a second-stage decoder circuit (4, 5, 6), which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits (A4 to A 7 ) of the input signal. The first-stage decoder circuit is formed by a threshold-operation type logic circuit (11) which carries out selection or non-selection by comparing the input signal (9a, 1 Oa) with a predetermined threshold level (VR), and the second-stage decoder circuit is formed by a diode-matrix circuit (D 5 to D 8 ).
摘要翻译：包括用于解码输入信号的高位（A0至A3）的第一级解码器电路（7-1至8-2,9,10,11）的双状态解码器电路和第二级解码器电路（4,5,6），其通过接收第一级解码器电路的选择的输出信号并且解码输入信号的低位（A4至A7）而被激活。第一级解码器电路由阈值操作型逻辑电路（11）构成，其通过将输入信号（9a，10a）与预定阈值电平（VR）进行比较来执行选择或不选择，级解码器电路由二极管矩阵电路（D5至D8）形成。

3. 发明公开

EP0020608A4 PROGRAMMABLE STORAGE/LOGIC ARRAY. 失效
标题翻译：可编程存储器/逻辑矩阵。
公开(公告)号：EP0020608A4
公开(公告)日：1981-03-24
申请号：EP79901588
申请日：1980-05-20
申请人： MASSACHUSETTS INST TECHNOLOGY
发明人： PATIL SUHAS S
IPC分类号： G06F7/00 , G06F7/50 , G06F7/505 , G06F7/506 , G11C17/00 , G11C17/14 , H03K19/177 , H04Q5/14 , G06F7/38 , G11C8/02
CPC分类号： G06F7/5057 , G11C17/00 , G11C17/14 , H03K19/17704

4. 发明授权

EP0166538B1 Two stage decoder circuit 失效
标题翻译：两级解码器电路
公开(公告)号：EP0166538B1
公开(公告)日：1991-07-24
申请号：EP85303790.1
申请日：1985-05-30
申请人： FUJITSU LIMITED
发明人： Okajima, Yoshinori
IPC分类号： G11C11/40 , H03M7/22 , G11C8/02
CPC分类号： G11C8/10 , H03M7/22

5. 发明公开

EP0166538A3 Two stage decoder circuit 失效
标题翻译：两级解码器电路
公开(公告)号：EP0166538A3
公开(公告)日：1989-01-25
申请号：EP85303790.1
申请日：1985-05-30
申请人： FUJITSU LIMITED
发明人： Okajima, Yoshinori
IPC分类号： G11C11/40 , H03M7/22 , G11C8/02
CPC分类号： G11C8/10 , H03M7/22
摘要： A two-state decoder circuit including a first-stage decoder circuit (7-1 to 8-2, 9, 10, 11), for decoding upper bits (Ao to A3) of an input signal, and a second-stage decoder circuit (4, 5, 6), which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits (A4 to A 7 ) of the input signal. The first-stage decoder circuit is formed by a threshold-operation type logic circuit (11) which carries out selection or non-selection by comparing the input signal (9a, 1 Oa) with a predetermined threshold level (VR), and the second-stage decoder circuit is formed by a diode-matrix circuit (D 5 to D 8 ).

6. 发明公开

EP1431678A4 FUNCTION SWITCHING METHOD, FUNCTION SWITCHING APPARATUS, DATA STORAGE METHOD, DATA STORAGE APPARATUS, DEVICE, AND AIR CONDITIONER 审中-公开
标题翻译：功能控制方法，功能的电路装置，数据存储方法，数据存储设备，设备和空调
公开(公告)号：EP1431678A4
公开(公告)日：2007-10-03
申请号：EP02799496
申请日：2002-09-24
申请人： DAIKIN IND LTD
发明人： USHIO TOSHINORI , YOSHISAKA KEIICHI , YAMAMOTO MITSUHIKO , YOKOI MASAAKI
IPC分类号： F24F11/00 , G11C8/02 , F24F11/02 , G06F9/06
CPC分类号： F24F11/83 , F24F11/54
摘要： An object of the present invention is to provide a technique capable of assembling a device in both of a first device performing a first function with a predetermined part and a second device performing a second function without a second part, and instructing each of the first and second functions. Determining means (92) determines the presence or absence of an electronic expansion valve (91) and gives the result to a central processing unit (93). The central processing unit (93) allows a gate array (94) operate and instruct a first function including a function of performing communication between a communication network (83) and an indoor unit (92a). When there is no electronic expansion valve (EV), the determining means (92) sends a result of the determination result indicative of the absence to the central processing unit (93). The central processing unit (93) instructs a second function of making the gate array (94) inoperative.

7. 发明公开

EP1447909A4 DATA HOLDING APPARATUS AND DATA READ OUT METHOD 有权
标题翻译： DATENHALTEVORRICHTUNG UND DATENAUSLESEVERFAHREN
公开(公告)号：EP1447909A4
公开(公告)日：2006-05-24
申请号：EP02803509
申请日：2002-11-15
申请人： ROHM CO LTD
发明人： FUJIMORI YOSHIKAZU
IPC分类号： G11C8/02 , G11C14/00 , H03K3/037
CPC分类号： G11C14/0072 , G11C14/00 , H03K3/0375
摘要： A data holding apparatus capable of holding data even when power supply is cut off and having a high reliability of data holding. A data holding apparatus (1) includes a data latch circuit (3) and a ferroelectric storage unit (5). In ferroelectric capacitors (17, 19), it is possible to store data in non-volatile manner. The ferroelectric capacitor (17) has one end connected via a transfer gate (11) to an input node (7a) of an inverter circuit (7). When data is passing, the transfer gate (11) is disconnected. Accordingly, even when the input data D changes during data passing, the change is rapidly transferred to the input node (7a). Consequently, the reliability of the latch operation is not lowered even when operated at normal operation speed.
摘要翻译：提供一种能够保持数据的数据保持装置，即使关闭电源并且保持数据的可靠性高。数据保持装置1设置有数据锁存电路3和铁电存储部5.铁电电容器17和19能够以非易失性的方式存储数据。铁电电容器17的一端通过传输门11与逆变器电路7的输入节点7a连接。当数据通过时，传输门11处于断开状态。因此，即使在数据通过时输入数据D发生变化，也能够将变化快速地传送到输入节点7a，所以即使以通常的速度进行操作，闭锁动作的可靠性也不会降低。

8. 发明公开

EP1540654A4 DISC WITH TEMPORARY DISC DEFINITION STRUCTURE (TDDS) AND TEMPORARY DEFECT LIST (TDFL), AND METHOD OF AND APPARATUS FOR MANAGING DEFECT IN THE SAME 有权转让
标题翻译：临时盘定义结构（TDDS）和临时缺陷列表（TDFL）和方法及装置缺陷管理IT媒体
公开(公告)号：EP1540654A4
公开(公告)日：2010-11-17
申请号：EP03784681
申请日：2003-08-11
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KO JUNG-WAN , LEE KYUNG-GEUN
IPC分类号： G11B20/12 , G11B7/004 , G11B7/0045 , G11B7/007 , G11B20/10 , G11B20/18 , G11C8/02
CPC分类号： G11B7/005 , G11B20/1883 , G11B2007/0013 , G11B2020/1873 , G11B2020/1893 , G11B2220/20 , G11B2220/218 , G11B2220/235 , G11B2220/2537

9. 发明公开

EP1643356A4 PARALLEL PROCESSING DEVICE AND PARALLEL PROCESSING METHOD 有权
标题翻译：并行处理设备和并行处理
公开(公告)号：EP1643356A4
公开(公告)日：2009-04-01
申请号：EP04711019
申请日：2004-02-13
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SHIMAMURA TOSHISHIGE , FUJII KOJI , SHIGEMATSU SATOSHI , MACHIDA KATSUYUKI , MORIMURA HIROKI
IPC分类号： G06F7/00 , G06F7/509 , G06F7/60 , G06K9/00 , G06K9/60 , G06K9/64 , G11C8/02
CPC分类号： G06K9/00006 , G06F7/5095 , G06F7/607 , G06K9/00986 , G06K9/6202 , G06K9/78 , G06K9/80
摘要： One of select signal lines (103) is selected by a select signal outputted from a row decode circuit (171) in relation to the row set by a row range setting section (172). The result of processing of the row by a processing circuit (102) is outputted to a data output line (104). The result of processing of a column set by a column range selecting section (105) is outputted to the data output line (104) and added by a column adder (106).

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