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1. 发明公开

EP2587485A1 A dual-port memory and a method thereof 审中-公开
标题翻译： Speicher mit doppeltem Anschluss und Verfahrendafür
公开(公告)号：EP2587485A1
公开(公告)日：2013-05-01
申请号：EP12187555.3
申请日：2012-10-08
申请人： Maishi Electronic (Shanghai) Ltd.
发明人： Zhang, Weihua , Yu, Mei
IPC分类号： G11C7/10 , G11C8/16 , G06F5/16
CPC分类号： G11C7/1075 , G11C8/16
摘要： A dual-port memory (200, 300) is provided. The dual-port memory includes a first single-port memory (202, 302) and a second single-port memory (201, 301). The first single-port memory is configured to store data in an even address of the dual-port memory. The second single-port memory is configured to store data in an odd address of the dual-port memory. The dual-port memory simultaneously performs a read operation to read data from the odd address and a write operation to write data into the even address in a first operation cycle. The dual-port memory thensimultaneously performs a read operation to read data from the even address and a write operation to write data into the odd address in a second operation cycle. The two operation cycles repeat alternately.
摘要翻译：提供双端口存储器（200,300）。双端口存储器包括第一单端口存储器（202,302）和第二单端口存储器（201,301）。第一个单端口存储器被配置为将数据存储在双端口存储器的偶数地址中。第二单端口存储器被配置为将数据存储在双端口存储器的奇数地址中。双端口存储器同时执行从奇数地址读取数据的读取操作和在第一操作周期中将数据写入偶数地址的写入操作。双端口存储器然后同时执行从偶数地址读取数据的读取操作和在第二操作周期中将数据写入奇数地址的写入操作。两个操作周期交替重复。

2. 发明公开

EP2587673A2 Signal input circuit/chip 审中-公开
标题翻译： Signaleingangsschaltung /片内
公开(公告)号：EP2587673A2
公开(公告)日：2013-05-01
申请号：EP12188704.6
申请日：2012-10-16
申请人： Maishi Electronic (Shanghai) Ltd.
发明人： Zhang, Weihua , Yu, Mei
IPC分类号： H03K19/173
CPC分类号： H03K19/1732
摘要： A signal input circuit and method and chip are disclosed. The signal input circuit (200) includes a control signal input terminal (201) configured for receiving a control signal (Control_pin); at least one common signal input terminal (23L) each configured for receiving a corresponding common signal (Common_pin[L]); at least one first signal output terminal (24L) each configured for outputting a corresponding first signal (First_sig[L]); at least one first signal unit (21L) each configured for receiving said corresponding common signal (Common_pin[L]) and outputting said corresponding common signal as said corresponding first signal (First_sig[L]) under control of said control signal (Control_pin); at least one second signal output terminal (25L) each configured for outputting a corresponding second signal (Second_sig[L]); and at least one second signal unit (22L) each configured for receiving said corresponding common signal (Common_pin[L]) and outputting said corresponding common signal (Common_pin[L]) as said corresponding second signal (Second_sig[L]) under control of said control signal.
摘要翻译：公开了一种信号输入电路及方法及芯片。信号输入电路（200）包括被配置为接收控制信号（Control_pin）的控制信号输入端子（201）。至少一个公共信号输入端子（23L），每个公共信号输入端子被配置用于接收相应的公共信号（Common_pin [L]）; 至少一个第一信号输出端子（24L），每个第一信号输出端子被配置为输出对应的第一信号（First_sig [L]）; 至少一个第一信号单元（21L），其被配置为在所述控制信号（Control_pin）的控制下接收所述对应的公共信号（Common_pin [L]）并输出所述对应的公共信号作为所述对应的第一信号（First_sig [L]）; 每个配置用于输出相应的第二信号（Second_sig [L]）的至少一个第二信号输出端子（25L）; 以及至少一个第二信号单元（22L），每个第二信号单元（22L）被配置为用于接收所述对应的公共信号（Common_pin [L]），并将所述对应的公共信号（Common_pin [L]）作为所述对应的第二信号（Second_sig [L] 所述控制信号。

3. 发明公开

EP2587489A1 Systems and methods for testing memories 审中-公开
标题翻译： Systeme und Verfahren zum Testen von Speichern
公开(公告)号：EP2587489A1
公开(公告)日：2013-05-01
申请号：EP12188620.4
申请日：2012-10-16
申请人： Maishi Electronic (Shanghai) Ltd.
发明人： Zhang, Weihua , Yu, Mei
IPC分类号： G11C29/56 , G11C29/08
CPC分类号： G11C29/56004 , G11C29/08 , G11C2029/0401 , G11C2029/2602 , G11C2029/5602
摘要： A system for testing a plurality of memories includes a plurality of memory testing devices and a controller. Each of the memory testing devices is coupled to one of the memories. The controller is configured to generate a test vector and send the test vector to the memory testing devices. Each of the memory testing devices tests its coupled memory respectively according to the test vector and sends a test result to the controller.
摘要翻译：用于测试多个存储器的系统包括多个存储器测试设备和控制器。每个存储器测试设备耦合到一个存储器。控制器被配置为生成测试向量并将测试向量发送到存储器测试设备。每个内存测试设备根据测试向量分别测试其耦合的内存，并将测试结果发送给控制器。

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