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1. 发明公开

EP0849803A3 Improvements in or relating to field effect transistors 失效
标题翻译：场效应晶体管或与之相关的改进
公开(公告)号：EP0849803A3
公开(公告)日：1999-12-22
申请号：EP97122525.5
申请日：1997-12-19
申请人： Texas Instruments Incorporated
发明人： Chen, Ih-Chin
IPC分类号： H01L29/06 , H01L21/331
CPC分类号： H01L29/66651 , H01L21/76202 , H01L29/0653 , H01L29/41766 , H01L29/41775 , Y10S438/969
摘要： A method for forming a transistor (50) includes forming a first insulating region (16) in the outer surface of a semiconductor body (10) and forming a second insulating region (16) in the outer surface of the semiconductor body (10) and spaced apart from the first insulating region by a region of semiconductor material. The method further includes planarizing the first and second insulating regions and the region of semiconductor material to define a planar surface (17) and forming a conductive source region (34) overlying the first insulating region. The method further includes forming a conductive drain region (36) overlying the second insulating region and forming a conductive gate body (24) overlying the planar surface (17) and spaced apart from the conductive source region (34) and the conductive drain region (36).
摘要翻译：一种用于形成晶体管（50）的方法包括：在半导体本体（10）的外表面中形成第一绝缘区域（16）;以及在半导体本体（10）的外表面中形成第二绝缘区域（16）;以及与第一绝缘区域隔开一半导体材料区域。该方法还包括平坦化第一绝缘区域和第二绝缘区域以及半导体材料区域以限定平坦表面（17）并形成覆盖第一绝缘区域的导电源极区域（34）。该方法进一步包括形成覆盖第二绝缘区域的导电漏极区域（36），并形成覆盖平坦表面（17）且与导电源极区域（34）和导电漏极区域（24）间隔开的导电栅极本体（24） 36）。

2. 发明公开

EP0768716A3 Bipolar transistor and fabrication method thereof 失效
公开(公告)号：EP0768716A3
公开(公告)日：1997-07-30
申请号：EP96116520.6
申请日：1996-10-15
申请人： NEC CORPORATION
发明人： Sato, Fumihiko
IPC分类号： H01L29/732 , H01L29/737 , H01L21/331
CPC分类号： H01L29/66287 , H01L29/66242 , H01L29/732 , H01L29/7378 , Y10S438/969
摘要： A semiconductor device including a bipolar transistor is provided, which can reduce the base resistance of the transistor. This device includes a semiconductor substructure having a first semiconductor active region of a first conductivity type in its inside. A first insulating layer is formed on the main surface of the substructure to cover the first active region. The first insulating layer has a first penetrating window exposing the first active region. A semiconductor contact region of a second conductivity type is formed on the first insulating layer. The contact region has an overhanging part which overhangs the first window. The second window is defined by the inner end of the overhanging part to be entirely overlapped with the first window. The contact region is made of a polycrystalline semiconductor. A second semiconductor active region of the second conductivity type is formed on the first active region in the first window. A semiconductor connection region of the second conductivity type is formed in the first window to surround the second active region. The connection region is contacted with the overhanging part of the contact region and the second active region, thereby electrically interconnecting the second active region with the contact region. The connection region is made of a polycrystalline semiconductor.

3. 发明公开

EP0466195A2 A fabrication method for semiconductor devices 失效
标题翻译： HerstellungsverfahrenfürHalbleiteranordnungen。
公开(公告)号：EP0466195A2
公开(公告)日：1992-01-15
申请号：EP91111743.0
申请日：1991-07-15
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Kameyama, Shuichi , Hori, Atsushi , Shimomura, Hiroshi , Segawa, Mizuki
IPC分类号： H01L21/331 , H01L21/20
CPC分类号： H01L29/66272 , H01L21/2022 , H01L21/2652 , H01L21/28525 , Y10S148/011 , Y10S148/124 , Y10S438/969
摘要： A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate (100). After forming a N-type semiconductor region (116) as the emitter by ion implanting, for instance, as into a P-type semiconductor region (106) as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region (116) and an amorphous silicon thin film (110) in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region (116), a single-crystalline silicon thin film (110A), and a polysilicon thin film (110B), thus forming a bipolar element having an emitter.
摘要翻译：连接多晶半导体薄膜和半导体区域的半导体器件的制造方法，该半导体器件包括在单晶半导体衬底中形成的高浓度杂质。在通过离子注入形成作为发射极的N型半导体区域之后，例如，作为基底的P型半导体区域，沉积多晶硅薄膜114，以便注入As离子，然后进行热处理。在这种情况下，通过固相外延生长来转变N型半导体区域的非晶部分和与其接触的非晶硅薄膜，从而形成单晶半导体区域，单晶硅薄膜和多晶硅薄膜，从而形成具有发射极的双极元件。

4. 发明公开

EP0208795A1 Method of fabricating a self-aligned metal-semiconductor FET 失效
标题翻译：制造具有金属 - 半导体接触的自对准的场效应晶体管的方法。
公开(公告)号：EP0208795A1
公开(公告)日：1987-01-21
申请号：EP85108694.2
申请日：1985-07-12
申请人： International Business Machines Corporation
发明人： Harder, Christoph Stephan, Dr. , Jaeckel, Heinz , Wolf, Hans Peter, Dr.
IPC分类号： H01L29/80 , H01L21/20
CPC分类号： H01L29/0891 , H01L29/812 , Y10S438/969
摘要： A method for the fabrication of self-aligned MESFET structures (30) with a recessed refractory submicron gate. After channel formation (32) on a SI substrate (31), which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing the refractory gate (33G) is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of e.g. GaAs using MOCVD or MBE processes resulting in poly-crystalline material over the gate "mask" and in mono-crystalline material (34S, 34D) on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes (35S, 35D). In order to further improve process reliability, insulating sidewalls (43-43) can be provided at the vertical edges of the gate (33G) to avoid source-gate and drain-gate shorts.

5. 发明公开

EP1256977A1 METHOD AND APPARATUS FOR PRODUCING POLYSILICON FILM, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：设备方法FÜRDIE HERSTELLUNG EINES POLYKRISTALLINEN SILIIUMFILMS
公开(公告)号：EP1256977A1
公开(公告)日：2002-11-13
申请号：EP00964741.3
申请日：2000-10-06
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA , Seiko Epson Corporation
发明人： OGAWA, Tetsuya, MITSUBISHI DENKI KABUSHIKI KAISHA , TOKIOKA, Hidetada, MITSUBISHI DENKI KABUSHIKI K. , NISHIMAE, Junichi, MITSUBISHI DENKI KABUSHIKI K. , OKAMOTO, Tatsuki, MITSUBISHI DENKI KABUSHIKI K. , SATO, Yukio, MITSUBISHI DENKI KABUSHIKI KAISHA , INOUE, Mitsuo, MITSUBISHI DENKI KABUSHIKI KAISHA , MIYASAKA, Mitsutoshi, SEIKO EPSON CORPORATION , JIROKU, Hiroaki, SEIKO EPSON CORPORATION
IPC分类号： H01L21/20 , C23C16/24
CPC分类号： C23C14/5813 , B23K26/0066 , B23K26/0604 , B23K26/0738 , B23K26/0838 , B23K26/352 , B23K2201/40 , B23K2203/52 , H01L21/02532 , H01L21/02678 , H01L21/02691 , H01L29/66757 , Y10S438/969
摘要： A process for a polycrystal silicon film is provided with the step of forming, on a glass substrate (31), an amorphous silicon film (33) having a first region (33a) and a second region (33b) that contacts this first region (33b), the step of forming a first polycrystal portion (34a) by irradiating the first region (33a) of the amorphous silicon film (33) with a laser (35) of which the wavelength is not less than 390 nm and not more than 640 nm and the step of forming a second polycrystal portion (34b) that contacts the first polycrystal portion (34a) by irradiating the second region (33b) and the portion of the region of the first polycrystal portion (34a) that contacts the second region (33b) of the amorphous silicon film (33) with the laser (35) of which the wavelength is not less than 390 nm and not more than 640 nm.
摘要翻译：提供了一种多晶硅膜的制造方法，在玻璃基板（31）上形成具有与该第一区域接触的第一区域（33a）和第二区域（33b）的非晶硅膜（33） 33b），通过用波长不小于390nm且不大于（nm）的激光（35）照射非晶硅膜（33）的第一区域（33a）形成第一多晶部分（34a）的步骤 640nm，通过照射第二区域（33b）和与第二区域（34a）接触的第一多晶部分（34a）的区域的部分形成与第一多晶部分（34a）接触的第二多晶部分（34b）的步骤，（33）的波长不小于390nm且不大于640nm的激光（35）的非晶硅膜（33b）。

6. 发明授权

EP0466195B1 A fabrication method for semiconductor devices 失效
标题翻译：用于半导体器件制造工艺
公开(公告)号：EP0466195B1
公开(公告)日：1999-05-19
申请号：EP91111743.0
申请日：1991-07-15
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Kameyama, Shuichi , Hori, Atsushi , Shimomura, Hiroshi , Segawa, Mizuki
IPC分类号： H01L21/331 , H01L21/20
CPC分类号： H01L29/66272 , H01L21/2022 , H01L21/2652 , H01L21/28525 , Y10S148/011 , Y10S148/124 , Y10S438/969

7. 发明公开

EP0704907A3 Bipolar transistor with a base layer having an extremely low resistance and method for fabricating the same 失效
标题翻译：具有极低电阻的基极层的双极型晶体管及其制造方法
公开(公告)号：EP0704907A3
公开(公告)日：1996-04-17
申请号：EP95115150.5
申请日：1995-09-26
申请人： NEC CORPORATION
发明人： Kato, Hiroshi, c/o NEC Corporation
IPC分类号： H01L29/737 , H01L29/10 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378 , Y10S438/969
摘要： A base region structure involved in a bipolar transistor, wherein the base region comprises a compound semiconductor epitaxial layer (7) formed in a recessed portion (5) provided by etching in an upper region of a semiconductor substrate (1) and the recessed portion (5) has a depth corresponding to a thickness of the compound semiconductor epitaxial layer (7) so that the base region has a top surface positioned at the same level as a top surface of the semiconductor substrate (1).
摘要翻译：一种涉及双极晶体管的基区结构，其中基区包括在半导体衬底（1）的上部区域中通过蚀刻提供的凹陷部分（5）中形成的化合物半导体外延层（7） 5）具有与所述化合物半导体外延层（7）的厚度相对应的深度，使得所述基极区具有与所述半导体基板（1）的顶表面位于相同水平的顶表面。

8. 发明授权

EP0083716B1 Process for forming III-V semiconductor MESFET devices, having self-aligned raised source and drain regions 失效
标题翻译：用于形成具有自对准提取源和漏区的III-V族半导体器件的方法
公开(公告)号：EP0083716B1
公开(公告)日：1988-02-03
申请号：EP82110810.7
申请日：1982-11-23
申请人： International Business Machines Corporation
发明人： Andrade, Thomas L.
IPC分类号： H01L21/203 , H01L29/80 , H01L29/08 , H01L29/64
CPC分类号： H01L29/0891 , H01L21/02395 , H01L21/02546 , H01L21/02631 , H01L21/02658 , H01L29/475 , H01L29/812 , Y10S148/088 , Y10S148/10 , Y10S148/105 , Y10S148/169 , Y10S438/969
摘要： A process for forming III-V semiconductor MESFET devices having self-aligned, raised source and drain regions is disclosed. A preferred embodiment relates to a process for forming gallium arsenide MESFET devices. A feature of the invention is placing a gate structure 5 on the gallium arsenide substrate 2. Then a process including molecular beam epitaxy, grows epitaxial gallium arsenide on each respective side of the gate 5, forming a raised source region 8 and a raised drain region 9. Gallium arsenide will not grow in a conductive state on top of the tungsten gate metal 5. The resulting MESFET device has a raised source 8 and drain 9 which significantly reduces the high resistance depleted surface adjacent to the gate which generally occurs in planar gallium arsenide MESFET devices. Furthermore, the MESFET channel region which is defined by the proximate edges of the source and the drain, is self-aligned with the edges of the gate by virtue of the insitu process for the formation of the source and drain, as described above.

9. 发明公开

EP0083716A2 Process for forming III-V semiconductor MESFET devices, having self-aligned raised source and drain regions 失效
标题翻译： Verfahren zur Herstellung von AIII Bs MESFETS miterhöhterSource und Drainzonen。
公开(公告)号：EP0083716A2
公开(公告)日：1983-07-20
申请号：EP82110810.7
申请日：1982-11-23
申请人： International Business Machines Corporation
发明人： Andrade, Thomas L.
IPC分类号： H01L21/203 , H01L29/80 , H01L29/08 , H01L29/64
CPC分类号： H01L29/0891 , H01L21/02395 , H01L21/02546 , H01L21/02631 , H01L21/02658 , H01L29/475 , H01L29/812 , Y10S148/088 , Y10S148/10 , Y10S148/105 , Y10S148/169 , Y10S438/969
摘要： A process for forming III-V semiconductor MESFET devices having self-aligned, raised source and drain regions is disclosed. A preferred embodiment relates to a process for forming gallium arsenide MESFET devices. A feature of the invention is placing a gate structure 5 on the gallium arsenide substrate 2. Then a process including molecular beam epitaxy, grows epitaxial gallium arsenide on each respective side of the gate 5, forming a raised source region 8 and a raised drain region 9. Gallium arsenide will not grow in a conductive state on top of the tungsten gate metal 5. The resulting MESFET device has a raised source 8 and drain 9 which significantly reduces the high resistance depleted surface adjacent to the gate which generally occurs in planar gallium arsenide MESFET devices. Furthermore, the MESFET channel region which is defined by the proximate edges of the source and the drain. is self- aligned with the edges of the gate by virtue of the insitu process for the formation of the source and drain, as described above.
摘要翻译：公开了一种用于形成具有自对准，升高的源极和漏极区域的III-V半导体MESFET器件的工艺。优选的实施方案涉及用于形成砷化镓MESFET器件的工艺。本发明的一个特征是将栅极结构5放置在砷化镓衬底2上。然后，包括分子束外延的工艺在栅极5的每个相应侧上生长外延砷化镓，形成升高的源极区8和升高的漏极区砷化镓在钨栅极金属5的顶部将不会在导电状态下生长。所得的MESFET器件具有升高的源极8和漏极9，其显着地减少了通常发生在平面镓中的与栅极相邻的高电阻耗尽表面砷化物MESFET器件。此外，如上所述，由源极和漏极的近边缘限定的MESFET沟道区域通过用于形成源极和漏极的本征工艺与栅极的边缘自对准。

10. 发明公开

EP0021393A1 Semiconductor device having pairs of vertical complementary bipolar transistors and method of fabrication therefor 失效
标题翻译：具有垂直互补双极晶体管对，和它们的制备方法的半导体器件。
公开(公告)号：EP0021393A1
公开(公告)日：1981-01-07
申请号：EP80103534.6
申请日：1980-06-24
申请人： International Business Machines Corporation
发明人： Silvestri, Victor J. , Tang, Denny D. , Wiedmann, Siegfried K.
IPC分类号： H01L21/82 , H01L27/02 , G11C11/40
CPC分类号： H01L21/82285 , G11C11/4113 , H01L21/743 , H01L21/763 , H01L27/0237 , Y10S438/969
摘要： A vertical pair (2) of complementary, bipolar transistors which includes a semiconductor substrate (8) of one conductivity type and a pair of dielectric isolation regions (9, 10) disposed in contiguous relationship with the substrate. An injector region (3) of opposite conductivity type is disposed between the pair of isolation regions (9, 10). A pair of heavily doped polycrystalline semiconductor regions (6, 5) of the one conductivity type is disposed over and in registry with the pair of isolation regions (9, 10). A single crystal semiconductor region (18) of the one conductivity type is disposed over and in registry with the injector region (3). Finally, a first zone (16) of opposite conductivity type is disposed in the single crystal region and a second zone (14) of the one conductivity type is disposed in the first zone (16). To form a memory cell, another vertical pair (2') of complementary, bipolar transistors like those just described is disposed in electrically isolated, spaced relationship with the first mentioned vertical pair (2) of complementary bipolar transistors. These pairs (2, 2') of transistors are arranged so that an isolation region (9) and a polycrystalline region (6) of each are common. To form the memory cell, the first and second zones (16,14; 16', 14') of each of the pairs are cross-coupied.
In addition, a method of manufacturing a semiconductor device having vertical complementary, bipolar transistors which includes the steps of forming regions (9,10) of dielectric isolation which are contiguous with a semiconductor substrate (8) and a region (3) of semiconductor of one conductivity type there-between, the semiconductor substrate (8) being of opposite conductivity type, forming regions (6, 5) of heavily doped, polycrystalline semiconductor of the opposite conductivity type and a region of single crystal semiconductor (18) of the opposite conductivity type in registry with the regions of dielectric isolation (9, 10) and the semiconductor region (18) of one conductivity type, respectively. The method also includes the step of forming a zone (16) of one conductivity type in the region (18) of singly crystal semiconductor and a zone (14) of opposite conductivity type in the zone (16) of one conductivity type. The method may be used to fabricate a buried injector memory cell.

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