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1. 发明公开

EP3378156A1 FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH INTEGRATED GATE CONNECTED DIODES 有权
公开(公告)号：EP3378156A1
公开(公告)日：2018-09-26
申请号：EP16801089.0
申请日：2016-11-08
申请人： Raytheon Company
发明人： BETTENCOURT, John P. , MALLAVARPU, Raghuveer
IPC分类号： H03F3/195 , H03F3/213 , H03F1/32 , H01L29/872 , H01L29/08
CPC分类号： H01L27/0629 , H01L21/8232 , H01L21/823437 , H01L21/823475 , H01L21/8252 , H01L29/0696 , H01L29/0891 , H01L29/1095 , H01L29/2003 , H01L29/47 , H01L29/7787 , H01L29/812 , H01L29/872 , H03F1/3205 , H03F1/3276 , H03F1/56 , H03F3/195 , H03F3/213 , H03F2200/126 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2200/75
摘要： A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

2. 发明公开

EP3316314A1 ALUMINUM-GALLIUM-NITRIDE COMPOUND/GALLIUM-NITRIDE HIGH-ELECTRON-MOBILITY TRANSISTOR 审中-公开
标题翻译：铝 - 镓 - 氮化物复合物/镓 - 氮化物高电子迁移率晶体管
公开(公告)号：EP3316314A1
公开(公告)日：2018-05-02
申请号：EP16881085.1
申请日：2016-12-23
申请人： China Electronics Technology Group Corporation No.55 Research Institute
发明人： REN, Chunjiang , CHEN, Tangsheng
IPC分类号： H01L29/778 , H01L29/06 , H01L29/08
CPC分类号： H01L29/7786 , H01L21/02378 , H01L21/02433 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/0257 , H01L21/02598 , H01L21/0262 , H01L21/02631 , H01L21/246 , H01L21/28575 , H01L21/28587 , H01L21/30621 , H01L29/06 , H01L29/0891 , H01L29/1029 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/401 , H01L29/41766 , H01L29/41775 , H01L29/454 , H01L29/475 , H01L29/66462 , H01L29/66863
摘要： The present invention discloses a nitride high electron mobility transistor having a strain balance of an aluminum gallium nitride insertion layer. According to one embodiment of the present invention, the transistor sequentially comprises: a substrate and a GaN buffer layer located on the substrate; an Al y Ga 1-y N insertion layer located on the GaN buffer layer; an Al x Ga 1-x N barrier layer located on the Al y Ga 1-y N insertion layer opposite to the GaN buffer layer; a GaN cap layer located on the Al x Ga 1-x N barrier layer; a "Γ"-shaped source electrode and drain electrode provided in recesses formed by the removal of the GaN cap layer and some thickness of the Al x Ga 1-x N barrier layer; and a gate electrode located between the source electrode and the drain electrode. According to another embodiment of the present invention, an Al z Ga 1-z N insertion layer is further included between the Al x Ga 1-x N barrier layer and the GaN cap layer. The advantages of the present invention are that the AlGaN insertion layer with a high Al content is used to achieve the function of the AlN insertion layer, leading to a stronger controllability of the process; and the incorporation of the "Γ"-shaped source electrode and drain electrode facilitates formation of an ohmic contact and the formation of an ohmic contact, combined with the GaN cap layer, enables better control for the overall stress on the epitaxial layer, thereby ensuring the reliability of the device and optimizing the performance of the device.
摘要翻译：本发明公开了具有铝镓氮插入层的应变平衡的氮化物高电子迁移率晶体管。根据本发明的一个实施例，晶体管依次包括：衬底和位于衬底上的GaN缓冲层; 位于GaN缓冲层上的AlyGa1-yN插入层; 位于与GaN缓冲层相对的AlyGa1-yN插入层上的AlxGa1-xN势垒层; 位于Al x Ga 1-x N势垒层上的GaN盖层; 设置在通过去除GaN盖层和一定厚度的Al x Ga 1-x N势垒层而形成的凹槽中的“Γ”形源电极和漏电极; 以及位于源电极和漏电极之间的栅电极。根据本发明的另一实施例，AlxGa1-xN势垒层和GaN帽层之间还包括AlzGa1-zN插入层。本发明的优点在于，Al含量高的AlGaN插入层用于实现AlN插入层的功能，使得该工艺的可控性更强; 并且“Γ”形源极电极和漏极电极的结合有助于形成欧姆接触并且形成与GaN顶盖层组合的欧姆接触，从而能够更好地控制外延层上的总体应力，从而确保设备的可靠性和优化设备的性能。

3. 发明授权

EP1815523B1 SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THEM 失效转让
标题翻译：半导体器件和方法及其
公开(公告)号：EP1815523B1
公开(公告)日：2016-09-14
申请号：EP05828962.0
申请日：2005-11-14
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： SUGIMOTO, Masahiro , UESUGI, Tsutomu , UEDA, Hiroyuki , SOEJIMA, Narumasa , KACHI, Tetsu
IPC分类号： H01L29/812 , H01L29/78 , H01L29/778 , H01L29/06 , H01L29/08 , H01L29/20 , H01L29/41
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0843 , H01L29/0847 , H01L29/0891 , H01L29/2003 , H01L29/41 , H01L29/778 , H01L29/7788 , H01L29/8122
摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

4. 发明授权

EP0741417B1 Heterostructure field effect device having refractory ohmic contact directly on channel layer and method of making 失效
$Heterostructure field effect device having refractory ohmic contact directly on channel layer and method of making$
标题翻译：具有直接形成在沟道层，高熔点的欧姆接触和制备方法上的异质结构场效应器件
公开(公告)号：EP0741417B1
公开(公告)日：1999-07-28
申请号：EP96106751.9
申请日：1996-04-29
申请人： MOTOROLA, INC.
发明人： Abrokwah, Jonathan K. , Huang, Jenn-Hwa , Ooms, William J. , Shurboff, Carl L. , Hallmark, Jerald A.
IPC分类号： H01L29/778 , H01L29/45 , H01L27/085 , H01L21/335
CPC分类号： H01L29/66462 , H01L21/28575 , H01L27/085 , H01L29/0891 , H01L29/41766 , H01L29/452

5. 发明公开

EP0744774A2 Field effect transistor and method for producing same 失效
标题翻译：场效应晶体管及其制造方法
公开(公告)号：EP0744774A2
公开(公告)日：1996-11-27
申请号：EP96108283.1
申请日：1996-05-23
申请人： MURATA MANUFACTURING CO., LTD.
发明人： Takashi, Murakawa, Murata Manufacturing Co., Ltd. , Hiroyuki, Nakano, Murata Manufacturing Co., Ltd.
IPC分类号： H01L29/417
CPC分类号： H01L29/66863 , H01L29/0891 , H01L29/41725 , H01L29/41775 , H01L29/8128
摘要： A field effect transistor includes: a semiconductor substrate; an active layer formed on a part of a principal surface of the semiconductor substrate and having a predetermined impurity concentration; and first and second heavily doped layers having an impurity concentration higher than the impurity concentration of the active layer formed in two respective areas of the principal surface of the semiconductor substrate, located on both sides of the active layer and in contact with the active layer. A gate electrode is formed on a surface of the active layer and a drain electrode and a source electrode are formed on respective surfaces of the first and second heavily doped layers. At least one of the drain electrode and the source electrode is formed so as to extend onto a surface of the active layer.

6. 发明公开

EP0642174A1 MESFET with low ohmic resistance 失效
标题翻译： MESFET mit Niederohmigem Widerstand。
公开(公告)号：EP0642174A1
公开(公告)日：1995-03-08
申请号：EP94112155.0
申请日：1994-08-03
申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Shiga, Nobuo, c/o Yokohama Works of Sumitomo
IPC分类号： H01L29/812 , H01L29/08 , H01L29/10
CPC分类号： H01L29/1029 , H01L29/0891
摘要： A field effect transistor of the present invention includes a semiconductor substrate (1), an active layer (2) formed by doping an impurity in a surface region of the semiconductor substrate, two heavily doped layers (3,4) formed respectively by doping the impurity at the two end portions of the active layer, a gate electrode (5) formed on the active layer to be in Schottky contact with the active layer, and source and drain electrodes (6,7) formed respectively on the two heavily doped layers to be in ohmic contact with the two heavily doped layers. The length W C of a portion where a gate-electrode-side portion of at least one of said source and drain electrodes and said heavily doped layer overlap each other is set with respect to a length W G of a portion where at least one of source- and drain-electrode-side edge portions of said gate electrode and said active layer overlap each other to satisfy 1[µm] + W G C G . For this reason, a drain current flowing in the gate-electrode-side edge portion of the source or drain electrode is distributed as compared to the prior art, thereby reducing the contact resistance of the source or drain electrode. Therefore, since the drain-source resistance in an ON state is reduced, the field effect transistor can be applied to a circuit which requires a high breakdown voltage as needed.
摘要翻译：本发明的场效应晶体管包括半导体衬底（1），通过在半导体衬底的表面区域掺杂杂质形成的有源层（2），分别通过掺杂形成的两个重掺杂层在有源层的两个端部的杂质，形成在与有源层肖特基接触的有源层上的栅电极（5）以及分别形成在两个重掺杂层上的源极和漏极与两个重掺杂层欧姆接触。源电极和漏电极中至少一个的栅电极侧部分和所述重掺杂层彼此重叠的部分的长度WC相对于源极 - 漏极电极中至少一个的部分的长度WG设定，并且所述栅电极和所述有源层的漏电极侧边缘部分彼此重叠以满足1±WG + WC <5WG。因此，与现有技术相比，分布在源极或漏极的栅电极侧边缘部分中的漏极电流，从而降低源极或漏极的接触电阻。因此，由于导通状态下的漏极 - 源极电阻降低，所以可以根据需要将场效应晶体管施加到需要高击穿电压的电路。

7. 发明公开

EP0598711A2 MESFET source/drain structure 失效
标题翻译： MESFET - 源极/漏极-Struktur。
公开(公告)号：EP0598711A2
公开(公告)日：1994-05-25
申请号：EP94200376.5
申请日：1989-11-29
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Oku, Tomoki, c/o Mitsubishi Denki Kabushiki Kaisha
IPC分类号： H01L29/812 , H01L29/08
CPC分类号： H01L29/66878 , H01L29/0891
摘要： A transistor (fig. 1(i)) having a refractory metal gate (3) on a semi-insulating compound semiconductor substrate (1), asymmetrical side walls (5',7') each side of the gate (3), a low concentration active channel (2) below the gate (3),
source and drain high concentration active regions (8a,8b) each side of the channel (2), and asymmetric intermediate concentration active regions (4a',4b') between source (8a) and channel (2), and channel (2) and drain (8b), respectively, beneath the asymmetrical side walls (5',7'). The side walls (5',7') may be removed.
摘要翻译：在半绝缘化合物半导体衬底（1）上具有难熔金属栅极（3）的晶体管（图1（i）），栅极（3）的每一侧的不对称侧壁（5'，7'），栅极（3）下方的低浓度有源沟道（2），沟道（2）的每一侧的源极和漏极高浓度有源区（8a，8b）和源极（2）之间的不对称中间浓度有源区（4a'，4b'）（8a）和通道（2），通道（2）和排水口（8b）分别位于不对称侧壁（5'，7'）的下方。侧壁（5'，7'）可以被移除。

8. 发明公开

EP0565054A2 N-type antimony-based strained layer superlattice and fabrication method 失效
标题翻译： N-typ-Antimonbasis-Übergitterstrukturmit Spannungsschicht und Verfahren zur Herstellung。
公开(公告)号：EP0565054A2
公开(公告)日：1993-10-13
申请号：EP93105687.3
申请日：1993-04-06
申请人： Hughes Aircraft Company
发明人： Hasenberg, Thomas C. , Brown, April S. , Larson, Lawrence E.
IPC分类号： H01L29/201 , H01L29/207 , H01L21/38 , H01L29/76 , H01L29/14 , H01L29/205
CPC分类号： H01L29/0847 , H01L21/28575 , H01L29/0891 , H01L29/155 , H01L29/66462 , H01L29/7783 , Y10S148/16 , Y10S438/938
摘要： High speed Group III-Sb materials are n-doped in a molecular beam epitaxy process by forming a superlattice with n-doped strained layers of a Group III-V compound upon Group III-Sb base layers. The base layers have lower conduction band energy levels than the strained layers, and allow doping electrons from the strained layers to flow into the base layers. The base layers preferably comprise Al x Ga 1-x Sb, while the strained layers preferably comprise a binary or ternary compound such as Al y Ga 1-y As having a single Group V component, where x and y are each from 0 to 1.0. The strained layers can be n-doped with silicon or tin, which would produce p-type doping if added directly to the base layers.
摘要翻译：通过在III-Sb基层上形成具有III-V族化合物的n掺杂应变层的超晶格，在分子束外延工艺中n掺杂高速III-Sb族材料。基层具有比应变层更低的导带能级，并允许从应变层掺杂电子流入基层。基层优选包含Al x Ga 1-x Sb，而应变层优选包含二元或三元化合物，例如具有单一V族组分的AlyGa1-yAs，其中x和y各自为0至1.0。应变层可以用硅或锡进行n掺杂，如果直接添加到基层，则会产生p型掺杂。

9. 发明公开

EP0392120A1 Semiconductor device with a gate having asymmetric sidewalls, and a production method thereof 失效
标题翻译：使用非对称的侧壁，以及它们的制备方法的半导体器件。
公开(公告)号：EP0392120A1
公开(公告)日：1990-10-17
申请号：EP89312417.2
申请日：1989-11-29
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Oku, Tomoki Mitsubishi Denki K. K. Optelectronic
IPC分类号： H01L29/60 , H01L29/812 , H01L21/28 , H01L29/10
CPC分类号： H01L29/66878 , H01L29/0891
摘要： A production method of a semiconductor device constituting a Schottky barrier gate type field effect transistor includes the steps of producing a low concentration active region at a desired position of a semi-insulating compound semiconductor substrate and producing a gate electrode comprising refractory metal on the active region, producing a first insulating film and etching the same thereby to produce first side wall assist films comprising the first insulating film at the both side walls of the gate electrode, removing one of the first side wall assist films at the side where a source electrode is to be produced by wet etching, plating a second insulating film to the thickness less than that of the first insulating film, etching the second insulating film thereby to produce a second side wall assist film having narrower width than that of the first side wall assist film at the side wall of the gate electrode at the side where the source electrode is to be produced, and conducting ion implantation with using the first and second side wall assist films and the gate electrode as a mask thereby to produce high concentration active regions in asymmetrical configurations at left and right at the both sides of the gate electrode.
摘要翻译：的半导体装置的构成的肖特基势垒栅型场效应晶体管的制造方法包括：在半绝缘化合物半导体衬底的所希望的位置产生一个低浓度活性区域并产生一栅电极上的有源区，其包括难熔金属的步骤，产生第一绝缘膜和蚀刻从而相同的，以产生第一侧壁辅助膜包括第一绝缘电影在栅电极的侧壁bothside，去除所述第一侧壁中的一个在其中源电极侧辅助膜通过湿法蚀刻来制造，电镀的第二绝缘膜的厚度小于所述第一绝缘膜，电影，蚀刻第二绝缘膜，从而产生第二侧壁辅助具有膜窄的宽度比第一侧壁的的辅助成膜在在一侧的栅电极的侧壁，其中所述源电极将被产生，并且导电离子注入使用所述第一和第二侧壁辅助膜和栅电极作为掩模，从而在栅电极的bothsides产生在左右不对称配置高浓度的有源区。

10. 发明授权

EP0083716B1 Process for forming III-V semiconductor MESFET devices, having self-aligned raised source and drain regions 失效
标题翻译：用于形成具有自对准提取源和漏区的III-V族半导体器件的方法
公开(公告)号：EP0083716B1
公开(公告)日：1988-02-03
申请号：EP82110810.7
申请日：1982-11-23
申请人： International Business Machines Corporation
发明人： Andrade, Thomas L.
IPC分类号： H01L21/203 , H01L29/80 , H01L29/08 , H01L29/64
CPC分类号： H01L29/0891 , H01L21/02395 , H01L21/02546 , H01L21/02631 , H01L21/02658 , H01L29/475 , H01L29/812 , Y10S148/088 , Y10S148/10 , Y10S148/105 , Y10S148/169 , Y10S438/969
摘要： A process for forming III-V semiconductor MESFET devices having self-aligned, raised source and drain regions is disclosed. A preferred embodiment relates to a process for forming gallium arsenide MESFET devices. A feature of the invention is placing a gate structure 5 on the gallium arsenide substrate 2. Then a process including molecular beam epitaxy, grows epitaxial gallium arsenide on each respective side of the gate 5, forming a raised source region 8 and a raised drain region 9. Gallium arsenide will not grow in a conductive state on top of the tungsten gate metal 5. The resulting MESFET device has a raised source 8 and drain 9 which significantly reduces the high resistance depleted surface adjacent to the gate which generally occurs in planar gallium arsenide MESFET devices. Furthermore, the MESFET channel region which is defined by the proximate edges of the source and the drain, is self-aligned with the edges of the gate by virtue of the insitu process for the formation of the source and drain, as described above.

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