专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0341461B1 Process for making a bipolar integrated circuit 失效
标题翻译：一种用于制造双极集成电路工艺。
公开(公告)号：EP0341461B1
公开(公告)日：1995-08-09
申请号：EP89107083.1
申请日：1989-04-20
申请人： MOTOROLA, INC.
发明人： Cambou, Bertrand F.
IPC分类号： H01L21/8222 , H01L21/76 , H01L29/72 , H01L21/74
CPC分类号： H01L29/0821 , H01L21/74 , H01L21/761 , H01L29/10 , H01L29/36 , Y10S148/011 , Y10S148/037

2. 发明公开

EP0472012A2 Method of boron diffusion into semiconductor wafers 失效
标题翻译：在Halbleiterwafern的Verfahren zur Bor扩散。
公开(公告)号：EP0472012A2
公开(公告)日：1992-02-26
申请号：EP91112736.3
申请日：1991-07-29
申请人： SHIN-ETSU HANDOTAI COMPANY LIMITED
发明人： Katayama, Masatake , Fujiya, Shoichi , Moroga, Isao , Shinomiya, Masaru
IPC分类号： H01L21/225 , H01L21/22
CPC分类号： H01L21/2254 , Y10S148/037 , Y10S438/909 , Y10S438/92
摘要： A method of diffusing boron into semiconductor wafers is disclosed which is made of essentially boron deposition and boron diffusion steps. The deposition step is performed from 900 to 1,000°C and the diffusion step at a temperature substantially equal to or higher than the temperature at the deposition step. Oxidation induced stacking faults are greatly reduced.
摘要翻译：公开了将硼扩散到半导体晶片中的方法，其基本上由硼沉积和硼扩散步骤制成。沉积步骤在900至1000℃下进行，扩散步骤在基本上等于或高于沉积步骤的温度的温度下进行。氧化引起的堆垛层错大大减少。

3. 发明授权

EP0099270B1 Method for the formation of buried gates of a semiconductor device 失效
标题翻译：用于形成半导体器件的栅极的方法
公开(公告)号：EP0099270B1
公开(公告)日：1990-02-28
申请号：EP83304079.3
申请日：1983-07-13
申请人： TOYO DENKI SEIZO KABUSHIKI KAISHA
发明人： Muraoka, Kimihiro
IPC分类号： H01L21/28 , H01L29/60
CPC分类号： H01L29/66416 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02639 , H01L21/2257 , H01L21/28 , H01L29/102 , H01L29/1066 , Y10S148/037 , Y10S148/039 , Y10S148/05 , Y10S148/088

4. 发明公开

EP0139266A3 A semiconductor integrated circuit device comprising an MOS transistor and a bipolar transistor and a manufacturing method of the same 失效
标题翻译：包含MOS晶体管和双极晶体管的半导体集成电路器件及其制造方法
公开(公告)号：EP0139266A3
公开(公告)日：1986-01-22
申请号：EP84111849
申请日：1984-10-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Iwasaki, Hiroshi c/o Patent Division
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L21/2257 , H01L21/8249 , H01L27/0623 , Y10S148/01 , Y10S148/032 , Y10S148/037 , Y10S148/038 , Y10S148/082 , Y10S148/123 , Y10S148/124
摘要： A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode (38, 39) of the field effect transistor and a collector electrode (40 2 ) of the bipolar transistor are formed from a common electrode layer (102) of a high impurity concentration, and in which the collector region (24 2 ) of the bipolar transistor comprises a region (100) of a high impurity concentration having a conductivity type the same as that of the collector region (24 2 ) of the bipolar transistor.

5. 发明公开

EP0145883A2 Method for minimizing autodoping during epitaxial deposition 失效
标题翻译：降低沉积外延层的自扩散的方法。
公开(公告)号：EP0145883A2
公开(公告)日：1985-06-26
申请号：EP84112380.5
申请日：1984-10-16
申请人： International Business Machines Corporation
发明人： Moksvold, Tor Wessberg
IPC分类号： H01L21/74
CPC分类号： H01L21/74 , H01L21/2205 , Y10S148/007 , Y10S148/01 , Y10S148/037 , Y10S148/145 , Y10S438/916
摘要： The method suggests the replacement of all or part of the solid or blanket buried region, typically a subcollector region of a bipolar transistor, by a mesh or stripe shaped subcollector. During subsequent thermal processing involving growth of the epitaxial layer, the stripes will at least partially merge, resulting in a solid subcollector. The method of minimizing autodoping implies only a special design of the subcollector mask. Therefore, there is no longer any need for technological changes either in the process or in the equipment. The method also applies to other buried layers, such as, subemitters, resistors, bottom isolation regions, etc.

6. 发明公开

EP0475051A3 Diffusion in semiconductor materials using a solid state source 失效
标题翻译：使用固体源的半导体材料的扩散
公开(公告)号：EP0475051A3
公开(公告)日：1992-06-17
申请号：EP91112752.0
申请日：1991-07-30
申请人： Hewlett-Packard Company
发明人： Chang, James S.C. , Carey, Kent A.W. , Williamson, James R. , Low, Thomas S.
IPC分类号： H01L21/225
CPC分类号： H01L21/2258 , Y10S148/015 , Y10S148/037
摘要： Method for deposit of a p type dopant from a dopant layer (24, 24a, 24b) into a predetermined region (25a, 25b) of a III-V semiconductor layer or multiple layers. The p type dopant is deposited in very high concentration in a semiconductor layer adjacent to the predetermined region. A second semiconductor layer (27, 27a, 27b), doped with a lower concentration of an n type dopant, is later deposited so that the high concentration p type dopant layer lies between the predetermined region and the n type dopant layer. The p type dopant is diffused into the predetermined region by thermally driven diffusion, which may be carried out at a lower temperature or for a shorter diffusion time interval than with conventional diffusion, and p type dopant diffusion may extend over greater distances.
摘要翻译：从掺杂剂层（24,24a，24b）沉积p型掺杂剂到III-V半导体层或多层的预定区域（25a，25b）中的方法。 p型掺杂剂以相当高的浓度沉积在与预定区域相邻的半导体层中。随后沉积掺杂有较低浓度的n型掺杂剂的第二半导体层（27,27a，27b），使得高浓度p型掺杂剂层位于预定区域和n型掺杂剂层之间。 p型掺杂剂通过热驱动扩散扩散到预定区域，其可以在比常规扩散更低的温度或更短的扩散时间间隔上进行，并且p型掺杂剂扩散可以在更大的距离上延伸。

7. 发明公开

EP0475051A2 Diffusion in semiconductor materials using a solid state source 失效
标题翻译：扩散在Halbleitermaterialien unter Verwendung einer Feststoffquelle。
公开(公告)号：EP0475051A2
公开(公告)日：1992-03-18
申请号：EP91112752.0
申请日：1991-07-30
申请人： Hewlett-Packard Company
发明人： Chang, James S.C. , Carey, Kent A.W. , Williamson, James R. , Low, Thomas S.
IPC分类号： H01L21/225
CPC分类号： H01L21/2258 , Y10S148/015 , Y10S148/037
摘要： Method for deposit of a p type dopant from a dopant layer (24, 24a, 24b) into a predetermined region (25a, 25b) of a III-V semiconductor layer or multiple layers. The p type dopant is deposited in very high concentration in a semiconductor layer adjacent to the predetermined region. A second semiconductor layer (27, 27a, 27b), doped with a lower concentration of an n type dopant, is later deposited so that the high concentration p type dopant layer lies between the predetermined region and the n type dopant layer. The p type dopant is diffused into the predetermined region by thermally driven diffusion, which may be carried out at a lower temperature or for a shorter diffusion time interval than with conventional diffusion, and p type dopant diffusion may extend over greater distances.
摘要翻译：从掺杂剂层（24,24a，24b）沉积p型掺杂剂到III-V半导体层或多层的预定区域（25a，25b）中的方法。 p型掺杂剂以相当高的浓度沉积在与预定区域相邻的半导体层中。随后沉积掺杂有较低浓度的n型掺杂剂的第二半导体层（27,27a，27b），使得高浓度p型掺杂剂层位于预定区域和n型掺杂剂层之间。 p型掺杂剂通过热驱动扩散扩散到预定区域，其可以在比常规扩散更低的温度或更短的扩散时间间隔上进行，并且p型掺杂剂扩散可以在更大的距离上延伸。

8. 发明公开

EP0319207A3 A method of producing a semi-conducteur device having a disordered superlattice 失效
标题翻译：生产具有障碍超导的半导体器件的方法
公开(公告)号：EP0319207A3
公开(公告)日：1989-09-06
申请号：EP88311187.4
申请日：1988-11-25
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Murakami, Takashi c/o Mitsubishi Denki K. K. , Otaki, Kaname c/o Mitsubishi Denki K. K. , Kumabe, Hisao c/o Mitsubishi Denki K. K.
IPC分类号： H01L21/225 , H01L33/00 , H01S3/19
CPC分类号： B82Y20/00 , H01L21/182 , H01S5/20 , H01S5/2059 , H01S5/34 , Y10S148/037 , Y10S148/095
摘要： A method of producing a semiconductor device such as a semiconductor laser having a controllably disordered superlattice. The superlattice (3) is grown epitaxially and in the same epitaxial growth process a heavily selenium doped semiconductor layer (7) is also grown in a known spatial relationship to the superlattice (3). The doped layer (7) is patterned as by etching and then the device is annealed to diffuse selenium impurities from the doped layer (7). The time and temperature of annealing are controlled such that the impurities diffuse into and thereby disorder regions (8) of the superlattice layer (3), leaving a non-disordered region (3) which can serve as a resonator in a laser.

9. 发明授权

EP0139266B1 A semiconductor integrated circuit device comprising an MOS transistor and a bipolar transistor and a manufacturing method of the same 失效
标题翻译：包含MOS晶体管和双极晶体管的半导体集成电路器件及其制造方法
公开(公告)号：EP0139266B1
公开(公告)日：1989-01-25
申请号：EP84111849.0
申请日：1984-10-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Iwasaki, Hiroshi c/o Patent Division
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L21/2257 , H01L21/8249 , H01L27/0623 , Y10S148/01 , Y10S148/032 , Y10S148/037 , Y10S148/038 , Y10S148/082 , Y10S148/123 , Y10S148/124

10. 发明公开

EP0159655A3 Method of forming a semiconductor structure having dielectrically isolated monocrystalline silicon regions 失效
标题翻译：形成具有电介质孤立单晶硅区域的半导体结构的方法
公开(公告)号：EP0159655A3
公开(公告)日：1987-03-04
申请号：EP85104594
申请日：1985-04-17
申请人： International Business Machines Corporation
发明人： Kinney, Wayne Irving , Lasky, Jerome Brett , Nesbit, Larry Alan
IPC分类号： H01L21/76 , H01L21/306
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/306 , H01L21/76264 , H01L21/7627 , H01L21/76281 , Y10S148/037 , Y10S148/051 , Y10S148/085 , Y10S148/086 , Y10S148/117
摘要： A method is provided for forming semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions (30) and a set of surface regions (50) having characteristics which make them anodically etch slower than the remaining portion of the silicon body (10). These two sets of regions define portions (32, 52, 62) in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions (50) from each other and the remaining portion (62) of the silicon body. Typically in a P-type silicon body the buried and surface regions (30, 50) are N-type regions formed through ion implantation. Using these N-type regions to control the exposure of the P-type material to the anodic etching solution and the formation of the porous silicon regions, a structure is obtained wherein surface monocrystalline silicon regions are isolated from the rest of the silicon body by a uniform layer of silicon dioxide (62) having a predetermined thickness.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式