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    • 7. 发明公开
    • PCB PROCESSING METHOD AND PCB
    • VERARBEITUNGSVERFAHRENFÜRLEITERPLATTE UND LEI​​TERPLATTE
    • EP3089562A1
    • 2016-11-02
    • EP14875182.9
    • 2014-05-21
    • ZTE Corporation
    • YI, BiMA, FengchaoREN, YonghuiXIONG, WangWANG, Yingxin
    • H05K1/00H05K3/04
    • H05K1/0298H05K1/09H05K1/115H05K3/0047H05K3/424H05K3/429H05K3/4611H05K3/4623H05K2201/10303H05K2203/0207H05K2203/16
    • The present invention discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB according to PCB design requirements, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present invention, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.
    • 本发明公开了一种PCB处理方法和PCB。 该方法包括:根据PCB设计要求分别在构成PCB的多个PCB子板上进行层压处理,以及对最顶层PCB子板进行钻孔和电镀以形成通孔; 并且将多个PCB子板层压在一起以形成PCB,并且对所形成的PCB进行钻孔和电镀以形成用于安装连接器的通孔,其中用于安装连接器的盲孔由通孔形成,并且深度 盲孔大于或等于连接器的信号引脚的长度。 由于本发明的技术方案,PCB的下层的晶片之间的空间可以加倍,并且晶片之间的布局空间可以加倍。