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1. 发明公开

EP3300276A1 METHOD, DEVICE AND SYSTEM FOR SENDING AND RECEIVING CODE BLOCK DATA STREAM 审中-公开
标题翻译：用于发送和接收代码块数据流的方法，设备和系统
公开(公告)号：EP3300276A1
公开(公告)日：2018-03-28
申请号：EP16820772.8
申请日：2016-06-28
申请人： Huawei Technologies Co., Ltd.
发明人： ZHONG, Qiwen , WU, Qiuyou
IPC分类号： H04L1/00
CPC分类号： H04J3/06 , H04J3/0691 , H04J2203/0085 , H04J2203/0094 , H04L1/00 , H04L1/0057 , H04L25/14 , H04L49/352
摘要： Embodiments of the present invention disclose a method for sending a code block data stream, including: adding m first data frames carrying the code block data stream to n physical layer data frames on an Ethernet physical interface, identifying a location of the first code block of each first data frame in the m first data frames by using an alignment marker of a physical layer data frame in the n physical layer data frames, and sending the n physical layer data frames that carry the m first data frames of the code block data stream, where m and n are integers greater than or equal to 1. According to the foregoing technical solution, there is no need to perform framing search in the first data frame, so as to improve efficiency in performing framing in the first data frame, reduce an overhead bit of the first data frame, and reduce system design complexity.
摘要翻译：本发明实施例公开了一种码块数据流的发送方法，包括：将m个携带码块数据流的第一数据帧添加到以太网物理接口上的n个物理层数据帧中，利用所述n个物理层数据帧中的物理层数据帧的对齐标记，将所述m个第一数据帧中的每个第一数据帧发送到所述n个物理层数据帧中，并发送携带所述m个代码块数据流的m个第一数据帧的n个物理层数据帧其中，m和n为大于等于1的整数。根据上述技术方案，不需要在第一数据帧中进行成帧搜索，以提高第一数据帧成帧的效率，减少第一个数据帧的开销位，并降低了系统设计的复杂性。

2. 发明授权

EP1720283B1 VIDEO/AUDIO NETWORK 有权
标题翻译：视频/音频网络
公开(公告)号：EP1720283B1
公开(公告)日：2017-08-23
申请号：EP06076427.1
申请日：2004-01-16
申请人： SONY UNITED KINGDOM LIMITED
发明人： Chen, Jian-Rong , Wilson, Daniel , Economou, Daphne
IPC分类号： H04L12/18 , H04L12/24 , H04L29/06
CPC分类号： H04L65/4076 , H04L12/185 , H04L29/06027 , H04L45/10 , H04L45/16 , H04L49/201 , H04L49/3009 , H04L49/351 , H04L49/352 , H04L49/602

3. 发明授权

EP2887596B1 Network device and information transmission method 有权
标题翻译：网络设备和信息传输过程
公开(公告)号：EP2887596B1
公开(公告)日：2016-10-26
申请号：EP14198659.6
申请日：2014-12-17
申请人： Huawei Technologies Co., Ltd.
发明人： Li, Jianzhao , Cao, Lu
IPC分类号： G06F13/42 , H04L12/933 , H04L12/931
CPC分类号： G06F13/4282 , H04L49/15 , H04L49/352
摘要： The present invention provides a network device and an information transmission method. The network device includes: a main control board and a service board, where the main control board includes a processor and a switching chip, and the service board includes a physical layer component. The switching chip is connected to the physical layer component by using a system bus. The system bus consists of a serializer/deserializer SerDes link. The system bus is configured to transmit service data and control information of a port of the physical layer component. The processor is configured to control the port of the physical layer component by using the control information of the port of the physical layer component. The network device provided in the present invention transmits the service data and the control information by using the system bus, so that the service board does not need to set a CPU processing the control information, thereby expanding an interface flexibly, and reducing device complexity and hardware costs.

4. 发明授权

EP2688243B1 50 Gb/s ethernet using serializer/deserializer lanes 有权
标题翻译：与50 GB以太网/ s，使用序列化和Deserialisierungsspuren
公开(公告)号：EP2688243B1
公开(公告)日：2015-03-18
申请号：EP13003128.9
申请日：2013-06-19
申请人： Broadcom Corporation
发明人： Masood, Burhan , Frazier, Howard
IPC分类号： H04L12/40 , H04L12/761 , H04L12/931 , G06F13/00
CPC分类号： H04L49/352 , G06F13/00 , H04L12/18 , H04L12/4013 , H04L45/16 , H04L45/44 , H04L49/00 , H04L49/25 , H04L49/351 , Y02D50/10
摘要： Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

5. 发明授权

EP1162788B1 Trunking and mirroring across stacked gigabit switches 有权
标题翻译：在“堆叠千兆”交流“中继”和“镜像”
公开(公告)号：EP1162788B1
公开(公告)日：2012-11-21
申请号：EP01305064.6
申请日：2001-06-11
申请人： Broadcom Corporation
发明人： Kalkunte, Mohan , Ambe, Shekhar , Kadambi, Shiri
IPC分类号： H04L12/46 , H04L12/44
CPC分类号： H04L47/2458 , H04L12/462 , H04L45/00 , H04L45/16 , H04L45/245 , H04L45/52 , H04L45/742 , H04L47/10 , H04L47/266 , H04L47/29 , H04L47/32 , H04L49/102 , H04L49/109 , H04L49/15 , H04L49/3009 , H04L49/3018 , H04L49/3036 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/506 , H04L49/508 , H04L49/602 , H04L69/22 , Y02D50/30
摘要： A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit. One of the first data port interface and the second data port interface is configured to determine forwarding information from a flexible length header for an incoming data packet received at a port of the one data port interface, and is configured to determine the forwarding information by shifting the information field positions read from the flexible length header.

6. 发明授权

EP2080328B1 NETWORK DIRECT MEMORY ACCESS 有权
标题翻译：网络直接内存访问
公开(公告)号：EP2080328B1
公开(公告)日：2012-06-27
申请号：EP07837039.2
申请日：2007-08-17
申请人： Apple Inc.
发明人： DESAI, Shailendra, S. , HAYTER, Mark, D. , GO, Dominic
IPC分类号： H04L12/56 , G06F13/28 , H04L29/08
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

7. 发明授权

EP1881656B1 Schaltungsstruktur zur Realisierung eines Knotens in einem Netzwerk zur Übertragung hochbitratiger, IP basierter Zeitmultiplexsignale, insbesondere einem Multi-Gigabit-Ethernet 有权
标题翻译：用于发送高比特率在网络中实现的节点的电路结构，基于IP的时分复用信号，特别是一个多千兆位以太网
公开(公告)号：EP1881656B1
公开(公告)日：2011-08-17
申请号：EP07011453.3
申请日：2007-06-12
申请人： ADVA AG Optical Networking
发明人： Hinderthür, Henning, Dr.
IPC分类号： H04L12/56
CPC分类号： H04L12/43 , H04L49/352

8. 发明授权

EP1241789B1 Network interface with double data rate and delay locked loop 有权
标题翻译：双倍数据速率和延迟锁定环网络接口
公开(公告)号：EP1241789B1
公开(公告)日：2011-06-01
申请号：EP02100218.3
申请日：2002-03-04
申请人： Broadcom Corporation
发明人： Lin, Jonathan , Jiang, Yong
IPC分类号： H03L7/081 , H04L12/413 , H04L7/00 , H04J3/06
CPC分类号： G06F13/385 , H03L7/0812 , H04J3/0697 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/40

9. 发明授权

EP1181791B1 APPARATUS FOR DISTRIBUTING A LOAD ACROSS A TRUNK GROUP 有权
标题翻译： DEVICE库容一行组分发
公开(公告)号：EP1181791B1
公开(公告)日：2009-12-02
申请号：EP00939327.3
申请日：2000-05-24
申请人： Broadcom Corporation
发明人： KALKUNTE, Mohan , KADAMBI, Shiri , AMBE, Shekhar
IPC分类号： H04L12/56
CPC分类号： H04L12/46 , H04L12/42 , H04L12/4625 , H04L12/56 , H04L12/5602 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/623 , H04L49/254 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/90 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , Y02D50/30
摘要： A network switch for network communications includes at least one first data port interface, wherein the a least one first data port interface supports a plurality of first data ports transmitting and receiving data at a first data rate. At least one second data port interface is provided, wherein the at least one second data port interface supports a plurality of second data ports transmitting and receiving data at a second data rate. A flow control unit is provided, wherein at least one of the first data ports and at least one of the second data ports are linked together with a plurality of ports on a second network switch forming a trunk group that is configured by the flow control unit to statistically distribute a data load transmitted across the trunk group.

10. 发明公开

EP2080328A2 NETWORK DIRECT MEMORY ACCESS 有权
标题翻译：网络直接内存访问
公开(公告)号：EP2080328A2
公开(公告)日：2009-07-22
申请号：EP07837039.2
申请日：2007-08-17
申请人： P. A. Semi, Inc.
发明人： DESAI, Shailendra, S. , HAYTER, Mark, D. , GO, Dominic
IPC分类号： H04L12/56 , G06F13/28 , H04L29/08
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

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