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1. 发明公开

EP3182584A1 PHASE TRACKING RECEIVER 审中-公开
标题翻译：相位跟踪接收机
公开(公告)号：EP3182584A1
公开(公告)日：2017-06-21
申请号：EP15201303.3
申请日：2015-12-18
申请人： Stichting IMEC Nederland
发明人： PURUSHOTHAMAN, Vijay Kumar , LIU, Yao-Hong , STASZEWSKI, Robert Bogdan
IPC分类号： H03D3/24
CPC分类号： H04L27/06 , H03D3/242 , H03L7/093 , H03L7/0991 , H03L7/101
摘要： This invention relates to a receiver comprising: a phase detector with a first and second input, the first input being adapted to receive a modulated input signal; a comparator comprising an input coupled to an output of the phase detector; a frequency-offset cancellation block comprising an input coupled to an output of the comparator. The receiver includes a digitally controlled oscillator comprising: a control input coupled to an output of the comparator and an output of the frequency-offset cancellation block; and an output coupled to the second input of the phase detector.
摘要翻译：本发明涉及一种接收机，包括：具有第一和第二输入端的相位检测器，第一输入端适于接收调制输入信号; 比较器，包括耦合到所述相位检测器的输出的输入; 频率偏移消除块，包括耦合到比较器的输出的输入。该接收器包括数字控制振荡器，该数字控制振荡器包括：耦合到比较器的输出端和频率偏移消除块的输出端的控制输入端; 以及耦合到相位检测器的第二输入的输出。

2. 发明公开

EP1756939A4 BURST MODE RECEIVER BASED ON CHARGE PUMP PLL WITH IDLE-TIME LOOP STABILIZER 审中-公开
标题翻译：基金会基金会系统钳位麻省理工学院LEERLAUFDREHSTELLER
公开(公告)号：EP1756939A4
公开(公告)日：2007-07-18
申请号：EP05760719
申请日：2005-06-14
申请人： MATISSE NETWORKS INC
发明人： SHACHAR SHLOMO , MOSHE OREN
IPC分类号： H03D3/24
CPC分类号： H03D3/241 , H03L7/07 , H03L7/0807 , H03L7/101 , H04L7/033
摘要： An improved burst mode receiver includes a digital phase detector, receiving an incoming signal. The receiver also includes a charge pump, receiving pulse signals from the digital phase detector to compare the incoming clock phase to the local generated clock phase and to control the charge pump, a loop filter, receiving a charge value from the charge pump and producing a control signal and a local clock generator, receiving the control signal, producing a recovered clock and supplying the recovered clock to the digital phase detector.
摘要翻译：改进的突发模式接收机包括数字相位检测器，接收输入信号。接收器还包括电荷泵，接收来自数字相位检测器的脉冲信号，以将输入时钟相位与本地产生的时钟相位进行比较，并控制电荷泵，环路滤波器，从电荷泵接收电荷值，并产生控制信号和本地时钟发生器，接收控制信号，产生恢复的时钟并将恢复的时钟提供给数字相位检测器。

3. 发明授权

EP2988425B1 DATA PROCESSING DEVICE WITH MODULE FOR DETECTION AND ELIMINATION OF LOCAL OSCILLATOR SIGNAL DEGRADATION 有权
标题翻译：具有用于检测和消除局部振荡信号衰减的模块的数据处理装置
公开(公告)号：EP2988425B1
公开(公告)日：2018-04-18
申请号：EP15181077.7
申请日：2015-08-14
申请人： NXP B.V.
发明人： Kerselaers, Anthony , Gommé, Liesbeth
IPC分类号： H04B1/14 , H04B1/04 , H04B1/28
CPC分类号： H04B1/1638 , H03B2201/03 , H03L7/085 , H03L7/095 , H03L7/101 , H04B1/0096 , H04B1/0475 , H04B1/14 , H04B1/28 , H04B17/29
摘要： One example discloses a data processing device, comprising: a local oscillator (LO) having an LO frequency output, an LO performance parameter output, and an LO frequency select input; and a degradation detection module, coupled to the LO performance parameter output and to the LO frequency select input, and including an LO frequency select module triggered by the LO performance parameter output. Another example discloses an article of manufacture comprises at least one non-transitory, tangible machine readable storage medium containing executable machine instructions for controlling a data processing device which comprise: monitoring a set of local oscillator (LO) performance parameters; setting an LO degraded state when at least one of the LO performance parameters is not within a predetermined range; and adjusting an LO frequency in response to the LO degraded state.

4. 发明公开

EP2903164A1 Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock 有权转让
标题翻译：装置和方法用于从软过渡相位控制电路保持在通过相位耦合新请求
公开(公告)号：EP2903164A1
公开(公告)日：2015-08-05
申请号：EP15153213.2
申请日：2015-01-30
申请人： Hittite Microwave Corporation
发明人： Allan, Gordan John , Fortier, Justin L.
IPC分类号： H03L7/14 , H03L7/10
CPC分类号： H03L7/08 , H03L7/10 , H03L7/101 , H03L7/14 , H03L7/143 , H03L7/146 , H03L7/23
摘要： Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal chosen from one or more reference clock signals. When the control circuit decides that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.
摘要翻译：中的装置和方法提供了一种用于锁相环路（PLL）。在某些配置中，时钟系统包括：一个PLL，控制电路，和一个故障保持电路也设置在PLL的环路滤波器的输入经由故障保持开关和可变电阻器电耦合到。所述控制电路生成基于来自一个或多个参考时钟信号中选择的选择的参考时钟信号的PLL输入时钟信号的速率。当控制电路判定没有所选择的参考时钟信号是不可靠的，则控制电路禁止PLL的反馈环路和接通开关保持模式。基准时钟信号被改变或以其他方式变为可靠之后，控制电路使PLL的反馈环路，同时保持故障保持开关接通，并控制可变电阻器超时的电阻，以提供到重新获得相位锁定从故障保持的软过渡。

5. 发明公开

EP2451081A1 PLL CIRCUIT, AND RADIO COMMUNICATION DEVICE EQUIPPED THEREWITH 审中-公开
标题翻译： PLL-SCHALTUNG UND DAMIT AUSGESTATTETE FUNKKOMMUNIKATIONSVORRICHTUNG
公开(公告)号：EP2451081A1
公开(公告)日：2012-05-09
申请号：EP10793826.8
申请日：2010-06-28
申请人： Semiconductor Components Industries, LLC , National University Corporation Gunma University
发明人： DAN, Toru , TANABE, Tomoyuki , KOBAYASHI, Haruo
IPC分类号： H03L7/107 , H03L7/06
CPC分类号： H03L7/1075 , H03L7/099 , H03L7/101 , H03L2207/50
摘要： In an ADPLL circuit 100, on the basis of a gain of a digitally controlled oscillator 10 estimated when a loop gain of a certain value is set in the loop filter 18 and on the basis of a device parameter of the digitally controlled oscillator 10, the DCO gain. estimation unit 20 estimates a gain of the digitally controlled oscillator 10 when a loop gain of another value is set in the loop filter 18,
摘要翻译：在ADPLL电路100中，基于在环路滤波器18中设定了某一值的环路增益并基于数字控制振荡器10的器件参数的情况下所估计的数字控制振荡器10的增益， DCO增益。当在环路滤波器18中设定另一个值的环路增益时，估计单元20估计数控振荡器10的增益，

6. 发明授权

EP2903164B1 Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock 有权转让
标题翻译：装置和方法用于从软过渡相位控制电路保持在通过相位耦合新请求
公开(公告)号：EP2903164B1
公开(公告)日：2016-08-24
申请号：EP15153213.2
申请日：2015-01-30
申请人： Hittite Microwave LLC
发明人： Allan, Gordan John , Fortier, Justin L.
IPC分类号： H03L7/14 , H03L7/10
CPC分类号： H03L7/08 , H03L7/10 , H03L7/101 , H03L7/14 , H03L7/143 , H03L7/146 , H03L7/23
摘要： Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal chosen from one or more reference clock signals. When the control circuit decides that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.

7. 发明公开

EP2988425A1 DATA PROCESSING DEVICE WITH MODULE FOR DETECTION AND ELIMINATION OF LOCAL OSCILLATOR SIGNAL DEGRADATION 有权
标题翻译： BESEITIGUNG EINER LOKALOSZILLATORSIGNALVERSCHLECHTERUNG DATENVERARBEITUNGSVORRICHTUNG MIT MODUR ZUR DETEKTION
公开(公告)号：EP2988425A1
公开(公告)日：2016-02-24
申请号：EP15181077.7
申请日：2015-08-14
申请人： NXP B.V.
发明人： Kerselaers, Anthony , Gommé, Liesbeth
IPC分类号： H04B1/14 , H04B1/04 , H04B1/28
CPC分类号： H04B1/1638 , H03B2201/03 , H03L7/085 , H03L7/095 , H03L7/101 , H04B1/0096 , H04B1/0475 , H04B1/14 , H04B1/28 , H04B17/29
摘要： One example discloses a data processing device, comprising: a local oscillator (LO) having an LO frequency output, an LO performance parameter output, and an LO frequency select input; and a degradation detection module, coupled to the LO performance parameter output and to the LO frequency select input, and including an LO frequency select module triggered by the LO performance parameter output. Another example discloses an article of manufacture comprises at least one non-transitory, tangible machine readable storage medium containing executable machine instructions for controlling a data processing device which comprise: monitoring a set of local oscillator (LO) performance parameters; setting an LO degraded state when at least one of the LO performance parameters is not within a predetermined range; and adjusting an LO frequency in response to the LO degraded state.
摘要翻译：一个实例公开了一种数据处理装置，包括：具有LO频率输出的本地振荡器（LO），LO性能参数输出和LO频率选择输入; 以及劣化检测模块，其耦合到LO性能参数输出和LO频率选择输入，并且包括由LO性能参数输出触发的LO频率选择模块。另一个实例公开了一种制品，包括至少一个非暂时的，有形的机器可读存储介质，其包含用于控制数据处理装置的可执行机器指令，其包括：监视一组本地振荡器（LO）性能参数; 当所述LO性能参数中的至少一个不在预定范围内时，设置LO降级状态; 以及响应于LO退化状态来调整LO频率。

8. 发明公开

EP2451081A4 PLL CIRCUIT, AND RADIO COMMUNICATION DEVICE EQUIPPED THEREWITH 审中-公开
标题翻译： PLL电路和如此装备的无线电通信设备
公开(公告)号：EP2451081A4
公开(公告)日：2014-10-29
申请号：EP10793826
申请日：2010-06-28
申请人： SEMICONDUCTOR COMPONENTS IND , UNIV GUNMA NAT UNIV CORP
发明人： DAN TORU , TANABE TOMOYUKI , KOBAYASHI HARUO
IPC分类号： H03L7/107 , H03L7/06 , H03L7/099
CPC分类号： H03L7/1075 , H03L7/099 , H03L7/101 , H03L2207/50

9. 发明公开

EP1756939A2 BURST MODE RECEIVER BASED ON CHARGE PUMP PLL WITH IDLE-TIME LOOP STABILIZER 审中-公开
标题翻译： Burstmodenempfängerauf Basis einer Ladungspumpen-PLL mit Leerlauf-Schleifenstabilisierung
公开(公告)号：EP1756939A2
公开(公告)日：2007-02-28
申请号：EP05760719.4
申请日：2005-06-14
申请人： Matisse Networks, Inc.
发明人： SHACHAR, Shlomo , MOSHE, Oren
IPC分类号： H03D3/24
CPC分类号： H03D3/241 , H03L7/07 , H03L7/0807 , H03L7/101 , H04L7/033
摘要： An improved burst mode receiver includes a digital phase detector, receiving an incoming signal. The receiver also includes a charge pump, receiving pulse signals from the digital phase detector to compare the incoming clock phase to the local generated clock phase and to control the charge pump, a loop filter, receiving a charge value from the charge pump and producing a control signal and a local clock generator, receiving the control signal, producing a recovered clock and supplying the recovered clock to the digital phase detector.
摘要翻译：改进的突发模式接收机包括数字相位检测器，接收输入信号。接收器还包括电荷泵，接收来自数字相位检测器的脉冲信号，以将输入时钟相位与本地产生的时钟相位进行比较，并控制电荷泵，环路滤波器，从电荷泵接收电荷值，并产生控制信号和本地时钟发生器，接收控制信号，产生恢复的时钟并将恢复的时钟提供给数字相位检测器。

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