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1. 发明公开

EP2073389A1 Method and apparatus for multi-mode clock data recovery 有权
标题翻译： Verfahren und Vorrichtung zur Mehrmoden-Takt- / Datenwiederherstellung
公开(公告)号：EP2073389A1
公开(公告)日：2009-06-24
申请号：EP09157226.3
申请日：2006-01-06
申请人： Altera Corporation
发明人： Shumarayev, Sergey , Patel, Rakesh H. , Wong, Wilson , Hoang, Tim T.
IPC分类号： H03L7/099 , H03L7/087 , H03L7/07 , H03L7/08 , H04L7/033 , H04L1/24
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： A method of generating a recovered clock signal for an application having a transmission frequency F and a consecutive identical digits requirement CID, the method comprising providing a multi-mode clock data recovery circuit comprising a phase detector, a frequency detector, a controlled oscillator, and a phase interpolator, operating the multi-mode clock data recovery circuit in a first mode if the quantity (CID/F) is less than a threshold time and operating the multi-mode clock data recovery circuit in a second mode if the quantity (CID/F) is greater than the threshold time. Corresponding apparatus is described.
摘要翻译：一种为具有传输频率F和连续相同数字要求CID的应用产生恢复的时钟信号的方法，所述方法包括提供多模式时钟数据恢复电路，其包括相位检测器，频率检测器，受控振荡器和相位插值器，如果数量（CID / F）小于阈值时间，则以第一模式操作多模式时钟数据恢复电路，并且在第二模式下操作多模式时钟数据恢复电路，如果数量（CID / F）大于阈值时间。描述相应的装置。

2. 发明授权

EP1159807B1 GEWINNUNG VON TAKTSIGNALEN ZUR ABTASTUNG VON DATENSIGNALEN UNTERSCHIEDLICHER DATENRATEN MIT HILFE EINES PHASENREGELKREISES 有权
标题翻译： COLLECTION时钟信号为不同的数据速率与相LOOP的帮助扫描数据信号
公开(公告)号：EP1159807B1
公开(公告)日：2008-03-05
申请号：EP00920367.0
申请日：2000-03-01
申请人： Nokia Siemens Networks GmbH & Co. KG
发明人： DAUTH, Fritz, Jörg
IPC分类号： H04L25/02 , H04L7/10 , H04J3/06
CPC分类号： H03L7/14 , H03L7/087 , H04J2203/0089 , H04L7/033 , H04L25/0262
摘要： During a synchronisation process carried out using a phase-locking loop (PLL), one data signal (cds, ds) after the other is sampled with a clock signal (ts) with different frequencies, these different frequencies being allocated to different transmission protocols. Said data signals are checked for the presence of protocol identification information (PID1...n) allocated to the selected clock signal (ts) until said protocol identification information (PID1...n) is detected. The frequency resolution of the phase-locking loop (PLL) is advantageously increased, which in turn improves the synchronisation of the clock signal (ts) with the data signal (ds).

3. 发明公开

EP1742359A1 Apparatus and method for clock data recovery having a recovery loop with separate proportional path 审中-公开
标题翻译：装置和时钟恢复的方法用含有恢复环路的单独比例路径
公开(公告)号：EP1742359A1
公开(公告)日：2007-01-10
申请号：EP06011778.5
申请日：2006-06-07
申请人： Altera Corporation
发明人： Wang, Shoujun , Mei, Haitao , Bereza, Bill , Kwasniewski, Ted
IPC分类号： H03K3/354 , H03L7/087 , H03L7/107
CPC分类号： H03K3/354 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03L7/087 , H03L7/0891 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/0995 , H03L7/113 , H03L7/14 , H03L7/18 , H04L7/0004 , H04L7/033
摘要： A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector (311), a charge pump (31), an RC loop filter (R,C), and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump (31) and loop filter (R,C) with stable second-order behavior, with the resistor (R) of the loop filter (R,C) serving as a proportional path. A separate proportional path (312) is also provided that provides phase detector output directly to a control input of the VCO, while the resistor (R) of the loop filter (R,C) is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path (312) may be activated to maintain second-order behavior.
摘要翻译：一种时钟数据恢复回路也可以在很宽范围的数据速率可以使用和维护二阶行为包括一个非线性（例如，开关式）相位检测器（311），一个电荷泵（31），RC回路的滤波（ R，C），和信号发生器（例如，电压控制振荡器（VCO））。在低数据速率下，环可以与所述电荷泵（31）和环路滤波器（R，C）具有稳定的二阶行为来操作，与电阻器的环路滤波器的（R）（R，C）作为比例路径。一个单独的比例路径（312）被设置成没有直接提供相位检测器输出到VCO的控制输入端，而电阻器的环路滤波器的（R）（R，C）因此旁路。作为增加数据率引起三阶效应，单独的比例路径（312）可被激活以保持二阶特性。

4. 发明授权

EP1076416B1 PHASE-LOCKED LOOP 有权
标题翻译：锁相环路
公开(公告)号：EP1076416B1
公开(公告)日：2005-11-23
申请号：EP99912054.6
申请日：1999-03-31
申请人： FUJITSU GENERAL LIMITED
发明人： NISHIMURA, Eizou Fujitsu General Limited , NAKAJIMA, Masamichi Fujitsu General Limited
IPC分类号： H03L7/14 , H03L7/191 , H03L7/089
CPC分类号： H03L7/191 , H03L7/14
摘要： A PLL comprises a phase comparator (20), a loop filter (21), a VCO (14), and a loop counter (22). The PLL further comprises a prediction window circuit (23) that produces HWIN (prediction window signal) for predicting positions where REF signals (standard signal) appear, and a loss compensation circuit (24) that detects the loss of the REF in the HWIN output and generates d.REFX (first corrective signal) for compensating for the loss and d.VARX (second corrective signal) for compensating for the phase difference between VAR (comparison signal) and d.REFX. If REF is lost, the phase comparator (20) performs appropriate compensation. If the phase difference between REF and VAR becomes close to zero, an accurate control voltage depending on the phase difference is supplied to a VCO by a gate control signal (Gc) that advances one clock pulse from the VAR phase.
摘要翻译： PLL包括相位比较器（20），环路滤波器（21），VCO（14）和环路计数器（22）。 PLL还包括产生用于预测REF信号（标准信号）出现的位置的HWIN（预测窗口信号）的预测窗电路（23）以及检测HWIN输出中的REF的损失的损耗补偿电路（24）并产生用于补偿损失的d.REFX（第一校正信号）和用于补偿VAR（比较信号）与d.REFX之间的相位差的d.VARX（第二校正信号）。如果REF失去，则相位比较器（20）执行适当的补偿。如果REF和VAR之间的相位差接近于零，则通过从VAR相位提前一个时钟脉冲的选通控制信号（Gc）将取决于相位差的准确控制电压提供给VCO。

5. 发明授权

EP1123580B1 CHARGE PUMP PHASE LOCKED LOOP CIRCUIT 有权
标题翻译：与电荷泵锁相环电路
公开(公告)号：EP1123580B1
公开(公告)日：2005-11-09
申请号：EP00961353.0
申请日：2000-08-24
申请人： Koninklijke Philips Electronics N.V.
发明人： NERON, Christophe
IPC分类号： H03L7/14 , H03L7/093
CPC分类号： G06F1/10 , H03L7/0891 , H03L7/095 , H03L7/14 , H04L7/0083 , H04L7/033

6. 发明授权

EP1341308B1 Phase locked loop 有权
公开(公告)号：EP1341308B1
公开(公告)日：2005-10-26
申请号：EP02256718.4
申请日：2002-09-26
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION
发明人： Yamagishi, Akihiro, NTT Intellectual Property Cntr , Tsukahara, Tsuneo, NTT Intellectual Property Cntr
IPC分类号： H03L7/089 , H03L7/14
CPC分类号： H03L7/0895 , H03L7/14 , H03L7/18

7. 发明公开

EP1444783A4 CASCADED DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：级联延迟线回路
公开(公告)号：EP1444783A4
公开(公告)日：2005-02-02
申请号：EP02773869
申请日：2002-10-23
申请人： MOTOROLA INC
发明人： JUAN JUI-KUO , STENGEL ROBERT E , MARTIN FREDERICK L , BOCKELMAN DAVID E
IPC分类号： H03L7/07 , H03L7/081 , H03L7/14 , H03L7/16 , H03H11/26
CPC分类号： H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
摘要： A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

8. 发明公开

EP1241791A3 PLL frequency synthesizer 有权
标题翻译： PLL频率合成器
公开(公告)号：EP1241791A3
公开(公告)日：2004-09-29
申请号：EP02250022.7
申请日：2002-01-03
申请人： FUJITSU LIMITED
发明人： Saito, Shinji, c/o Fujitsu VLSI Limited
IPC分类号： H03L7/14 , H03L7/089
CPC分类号： H03L7/0895 , H03L7/0891 , H03L7/093 , H03L7/14 , H03L7/18
摘要： A PLL frequency synthesizer (1) is provided with a switch circuit (10) interposed between a low-pass filter circuit (103) and a voltage-controlled oscillator (104). The switch circuit (10) is controlled based on a control signal (Sent) to open/close control a feedback loop lying between the low-pass filter circuit (103) and the voltage-controlled oscillator (104). Namely, the switch circuit (10) is opened according to a path-opening instruction of a feedback loop based on the control signal (Scnt) to open the feedback loop, thereby stopping the operation of the feedback loop. If this stop operation is controlled according to the control signal (Sent) so as to be carried out during a period in which a pseudo correction pulse is outputted from a charge pump circuit (102) for each phase comparison cycle of a phase comparator (101), then spurious generation incident to the pseudo correction pulse can be suppressed. In this way even a spurious characteristic in a lock state can be improved while ensuring a high-speed lockup characteristic to thereby implement satisfactory communication quality.

9. 发明公开

EP1444783A2 CASCADED DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：级联延迟线回路
公开(公告)号：EP1444783A2
公开(公告)日：2004-08-11
申请号：EP02773869.9
申请日：2002-10-23
申请人： MOTOROLA, INC.
发明人： JUAN, Jui-Kuo , STENGEL, Robert, E. , MARTIN, Frederick, L. , BOCKELMAN, David, E.
IPC分类号： H03L1/00
CPC分类号： H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
摘要： A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

10. 发明授权

EP0898372B1 Verfahren und Vorrichtung zum Einstellen der Schwingfrequenz eines Oszillators 失效
标题翻译：用于调节振荡器的振荡频率的方法和装置
公开(公告)号：EP0898372B1
公开(公告)日：2003-11-12
申请号：EP98113936.3
申请日：1998-07-24
申请人： Infineon Technologies AG
发明人： Heinen, Stefan , Beyer, Stefan
IPC分类号： H03L7/089 , H03L7/14
CPC分类号： H03L7/14 , H03L7/0895 , H03L7/095

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