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1. 发明公开

EP2903164A1 Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock 有权转让
标题翻译：装置和方法用于从软过渡相位控制电路保持在通过相位耦合新请求
公开(公告)号：EP2903164A1
公开(公告)日：2015-08-05
申请号：EP15153213.2
申请日：2015-01-30
申请人： Hittite Microwave Corporation
发明人： Allan, Gordan John , Fortier, Justin L.
IPC分类号： H03L7/14 , H03L7/10
CPC分类号： H03L7/08 , H03L7/10 , H03L7/101 , H03L7/14 , H03L7/143 , H03L7/146 , H03L7/23
摘要： Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal chosen from one or more reference clock signals. When the control circuit decides that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.
摘要翻译：中的装置和方法提供了一种用于锁相环路（PLL）。在某些配置中，时钟系统包括：一个PLL，控制电路，和一个故障保持电路也设置在PLL的环路滤波器的输入经由故障保持开关和可变电阻器电耦合到。所述控制电路生成基于来自一个或多个参考时钟信号中选择的选择的参考时钟信号的PLL输入时钟信号的速率。当控制电路判定没有所选择的参考时钟信号是不可靠的，则控制电路禁止PLL的反馈环路和接通开关保持模式。基准时钟信号被改变或以其他方式变为可靠之后，控制电路使PLL的反馈环路，同时保持故障保持开关接通，并控制可变电阻器超时的电阻，以提供到重新获得相位锁定从故障保持的软过渡。

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