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    • 1. 发明公开
    • ELECTRONIC APPARATUS HAVING A SERIAL AND DIGITAL TRANSMISSION OUTPUT AND DEVICE FOR MEASURING ELECTRIC QUANTITIES COMPRISING SAID ELECTRONIC APPARATUS
    • EP3393042A1
    • 2018-10-24
    • EP18166010.1
    • 2018-04-06
    • D.E.M. S.p.A.
    • Berton, Mattia
    • H03K17/687H03K17/693G06F13/40
    • H03K17/6874H03K17/693
    • The present disclosure relates to an electronic apparatus (1) having a serial and digital transmission output which comprises a processing unit (2), an output clamp (3) comprising first, second and third output terminals (31, 32, 33), said first terminal being an output terminal configured to emit a digital signal (Digit); a serial line (4), comprising first and second serial data lines (41,42) and a ground line (43). The electronic apparatus (1) is characterized by comprising a switch device (5), in signal communication with said processing unit (2), said switch device (5) comprising a first electronic switch (6) and a second electronic switch (7), wherein one end of said first electronic switch (6) is electrically connected with a first serial data line (41) and the other end of said first electronic switch (6) is electrically connected with said first terminal (31) of said output clamp (3), wherein one end of said second electronic switch (7) is electrically connected with the end of the first electronic switch (6) that is electrically connected with said first terminal (31) of the output clamp (3) and the other end of said second electronic switch (7) is electrically connected with said third terminal (33) of said output clamp (3), said second serial data line (42) is electrically connected with said second terminal (32) of said output clamp (3), said ground line (43) is electrically connected with said third terminal (33) of said output clamp (3),
      - said processing unit (2) generates a control signal (V) which is configured:
      - to cause said first electronic switch (6) to switch to the closed configuration and to cause the second electronic switch (7) to switch to the open configuration, so that said first line (41) of the serial line (4) will be on the first terminal (31) of the output clamp (3);
      - to cause said first electronic switch (6) to switch to the open configuration and to cause the second electronic switch (7) to switch to the open or closed configuration, so that said digital signal (Digit) will be on said first terminal (31) of the output clamp (3) in the open or closed state respectively.
    • 6. 发明公开
    • Switch controls
    • Schaltersteuerungen
    • EP2908435A1
    • 2015-08-19
    • EP14156704.0
    • 2014-02-26
    • ACCO
    • Cam, HervéVenec, StephanieDos Santos, Filipe
    • H03K17/693H03K17/10H04B1/48
    • H03K17/687H01Q1/50H01Q13/02H03D7/125H03K17/102H03K17/6874H03K17/693H03K2217/0054H04B1/006H04B1/44H04B1/48H04M1/72519H04W24/00
    • Switches for use in RF devices are provided that offer a better balance of power losses and switching times than switches of the prior art. Switches of the present invention comprise a stack of transistors controlled a symmetric bias network. The stack of transistors includes an even number of transistors arranged in series, where every two successive transistors defines a pair. The bias network includes a symmetrically branching set of connections, where the gates of every pair of transistors are connected by a first connection having a first node, and two or more first nodes are connected by a second connection to a second node, and so forth. The symmetry of the bias network tends to reject even harmonics, and the rejection of even harmonics can be further enhanced by adding capacitors between the bias network and the stack of transistors at points of symmetry.
    • 提供了用于RF装置的开关,其提供比现有技术的开关更好地平衡功率损耗和开关时间。 本发明的开关包括控制对称偏压网络的晶体管堆叠。 晶体管堆叠包括串联布置的偶数个晶体管,其中每两个连续的晶体管定义一对。 偏置网络包括对称分支的连接集合,其中每对晶体管的栅极通过具有第一节点的第一连接连接,并且两个或更多个第一节点通过第二连接连接到第二节点,等等 。 偏置网络的对称倾向于抑制偶次谐波,并且可以通过在对称点处在偏置网络和晶体管堆叠之间添加电容器来进一步增强平均谐波的抑制。
    • 10. 发明公开
    • TRANSFER GATE CIRCUIT, AND POWER COMBINING CIRCUIT, POWER AMPLIFYING CIRCUIT, TRANSMISSION DEVICE, AND COMMUNICATION DEVICE USING THE TRANSFER GATE CIRCUIT
    • 过渡门电路和性能组合切换,电源升压电路,发送装置和通信设备与过渡门电路
    • EP2461483A1
    • 2012-06-06
    • EP10804152.6
    • 2010-03-30
    • Kyocera Corporation
    • NAGAYAMA,AkiraFUKUOKA,YasuhikoIGARASHI,SadaoISOYAMA,Shinji
    • H03K17/693H03F3/68
    • H03F3/193H03F3/245H03F3/3028H03F2200/387H03F2200/451H03F2203/30078H03F2203/30114H03K17/6874H03K17/693
    • Provided are a transfer gate circuit that has reduced disturbance in an output waveform thereof, a power combining circuit using the transfer gate circuit, and a transmission device and a communication device that use the power combining circuit. The transfer gate circuit includes: output terminals (3, 4) ; a transistor (5) including a drain connected to the output terminal (3); a transistor (6) including a drain connected to the output terminal (4); transistors (7, 8) each including a drain connected to the output terminal (3) and each including a source connected to a ground potential; and transistors (9, 10) each including a drain connected to the output terminal (4) and each including a source connected to the ground potential. In the transfer gate circuit, the transistors (5, 6) include sources to which first and second input signals are input, respectively, the transistor (5) includes a gate to which a signal in phase with the second input signal is input, the transistor (6) includes a gate to which a signal in phase with the first input signal is input, the transistors (7, 9) each include a gate to which a signal in antiphase to the second input signal is input, and the transistors (8, 10) each include a gate to which a signal in antiphase to the first input signal is input.
    • 提供的是一个传输门电路也已在输出波形的扰动减少它们的功率使用传输门电路的组合电路,以及发送装置和通信装置没有使用功率组合电路。 传输门电路包括:输出端子(3,4); 包括连接到所述输出端子(3)的漏极的晶体管(5); 包括连接到所述输出端子(4)的漏极的晶体管(6); 晶体管(7,8)的每个包括连接到所述输出端子(3)的漏极和每个包括连接到接地电位的源; 和晶体管(9,10)的每个包括连接到所述输出端子(4)的漏极,并且每个包括连接到接地电位的源极。 在传输门电路中,晶体管(5,6)包括源到其中第一和第二输入信号被输入,分别,晶体管(5)包括一个栅极连接到哪个相位与所述第二输入信号的信号被输入时, 晶体管(6)包括一个栅极连接到哪个相位与所述第一输入信号的信号被输入时,晶体管(7,9)的每一个包括栅极,以其中在反相位的第二输入信号的信号被输入,并且晶体管( 8,10)的每一个包括栅极,以其中在反相位的第一输入信号的信号输入。