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1. 发明公开

EP1751853A1 A TUNEABLE CIRCUIT FOR CANCELING THIRD ORDER MODULATION 审中-公开
标题翻译：可调电路匹克第三高阶调制
公开(公告)号：EP1751853A1
公开(公告)日：2007-02-14
申请号：EP05748731.6
申请日：2005-05-12
申请人： Sirific Wireless Corporation
发明人： MANKU, Tajinder
IPC分类号： H03F1/32 , H03K5/01 , H04B1/38 , H04B15/06 , H04B1/12 , H03F3/18 , H03D1/02 , H03C1/06
CPC分类号： H03K5/1252 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03F1/3211 , H03F1/3223 , H03F3/24 , H03F3/45183 , H03F2200/372 , H03F2200/87 , H03F2203/45318 , H03F2203/45366 , H03F2203/45498 , H03F2203/45544 , H03K5/02 , H04B1/0475 , H04B1/123 , H04B2001/0441
摘要： A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.

2. 发明公开

EP3021483A1 AMPLIFIER AND RELATED METHOD 有权
标题翻译： VERSTÄRKERUNDZUGEHÖRIGESVERFAHREN
公开(公告)号：EP3021483A1
公开(公告)日：2016-05-18
申请号：EP15192244.0
申请日：2015-10-30
申请人： MediaTek, Inc
发明人： Yu, Chi-Yao , Chou, Chung-Yun
IPC分类号： H03F3/193 , H03F3/72 , H03F1/02 , H03F1/22 , H03F3/21 , H03F3/68
CPC分类号： H03F3/193 , H03F1/0277 , H03F1/223 , H03F3/211 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/129 , H03F2200/144 , H03F2200/294 , H03F2200/451 , H03F2200/54 , H03F2200/75 , H03F2200/87 , H03F2203/21142 , H03F2203/21154 , H03F2203/21175 , H03F2203/7206 , H03F2203/7236 , H04B1/04 , H04B2001/0416
摘要： An amplifier (400, 700) applicable to an intra-band non-contiguous carrier aggregation (NCCA) band includes a first amplifier circuit (401, 701) and a second amplifier circuit (402, 702). The NCCA band includes at least a primary component carrier (PCC) channel and a secondary component carrier (SCC) channel not adjacent to each other. The first amplifier circuit (401, 701) receives a first input signal (S1), and generates a first output signal (OUT1) for undergoing down-conversion of one of the PCC channel and the SCC channel. The second amplifier circuit (402, 702) receives at least one second input signal (S2), and generates a second output signal (OUT2) for undergoing down-conversion of another of the PCC channel and the SCC channel. The at least one second input signal (S2) received by the second amplifier circuit (402, 702) is provided by the first amplifier circuit (401, 701) according to the first input signal (Sl).
摘要翻译：适用于带内非连续载波聚合（NCCA）频带的放大器（400,700）包括第一放大器电路（401,701）和第二放大器电路（402,702）。 NCCA频带至少包括主分量载波（PCC）信道和不相邻的辅分量载波（SCC）信道。第一放大器电路（401,701）接收第一输入信号（S1），并产生用于经历PCC信道和SCC信道之一的下变频的第一输出信号（OUT1）。第二放大器电路（402,702）接收至少一个第二输入信号（S2），并产生用于经历PCC信道和SCC信道中的另一个的下变频的第二输出信号（OUT2）。由第二放大电路（402,702）接收的至少一个第二输入信号（S2）由第一放大电路（401,701）根据第一输入信号（S1）提供。

3. 发明公开

EP3214759A4 ULTRA-LOW WORKING VOLTAGE RAIL TO RAIL OPERATIONAL AMPLIFIER AND DIFFERENTIAL INPUT AMPLIFICATION-STAGE CIRCUIT AND OUTPUT-STAGE CIRCUIT THEREOF 无效
公开(公告)号：EP3214759A4
公开(公告)日：2018-02-28
申请号：EP15854770
申请日：2015-10-27
申请人： HUAWEI TECH CO LTD
发明人： TANG YANGYANG , ZHANG CHENXIONG
IPC分类号： H03F3/45 , H03F1/34 , H03F1/38
CPC分类号： H03F1/0205 , H03F1/38 , H03F3/45183 , H03F3/45219 , H03F3/45273 , H03F2200/135 , H03F2200/153 , H03F2200/513 , H03F2200/87 , H03F2203/45028 , H03F2203/45036 , H03F2203/45051 , H03F2203/45054 , H03F2203/45114 , H03F2203/45124 , H03F2203/45134 , H03F2203/45221 , H03F2203/45281 , H03F2203/45288 , H03F2203/45342
摘要： A differential input amplification-stage circuit (100) includes a voltage unit (10), first and second bulk-driven transistors (20, 30), first and second mirror current sources (40, 50), and a differential amplifier unit (60). The voltage unit (10) includes first to third voltage output ends (11, 12, 13). The first voltage output end (11) is connected to the first and the second bulk-driven transistors (20, 30); the first and the second bulk-driven transistors (20, 30) respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents; the differential amplifier unit (60) separately outputs first and second adjustment currents under an action of voltages of the first to the third voltage output ends (11, 12, 13); and the first and the second mirror current sources (40, 50) respectively output first and second predetermined currents (I out+ , I out- ) according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit (100). Therefore, output stability is improved. In addition, an output-stage circuit (200) and an ultra-low working voltage rail-to-rail transportation amplified circuit (300) are further provided.

4. 发明公开

EP2913922A1 A low noise amplifier circuit 审中-公开
标题翻译： RauscharmeVerstärkerschaltung
公开(公告)号：EP2913922A1
公开(公告)日：2015-09-02
申请号：EP14157220.6
申请日：2014-02-28
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Sivonen, Pete , Jussila, Jarkko , Vilhonen, Sami
IPC分类号： H03F3/193 , H03F1/22 , H03F1/26
CPC分类号： H03F1/56 , H03F1/223 , H03F1/26 , H03F3/193 , H03F3/265 , H03F2200/222 , H03F2200/294 , H03F2200/387 , H03F2200/451 , H03F2200/489 , H03F2200/54 , H03F2200/87 , H04B1/1036
摘要： An amplifier (300) for converting a single-ended input signal (V IN ) to a differential output signal (I OUT+ , I OUT- ). The amplifier (300) comprises a first transistor (301), a second transistor (302), a third transistor (303) and a fourth transistor (304). The first transistor (301), configured in common-source or common-emitter mode, receives the single-ended input signal and generate a first part of the differential output signal. The second transistor (302), also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistor (303,304) are capacitively cross-coupled. The amplifier (300) further comprises inductive degeneration such that a source or emitter of the first transistor (301) is connected to a first inductor (321) and a source or emitter of the second transistor (302) is connected to a second inductor (322).
摘要翻译：用于将单端输入信号（V IN）转换为差分输出信号（I OUT +，I OUT-）的放大器（300）。放大器（300）包括第一晶体管（301），第二晶体管（302），第三晶体管（303）和第四晶体管（304）。以共源或共发射模式配置的第一晶体管（301）接收单端输入信号并产生差分输出信号的第一部分。也配置在共源或共发射极模式的第二晶体管（302）产生差分输出信号的第二部分。第三和第四晶体管（303,304）电容交叉耦合。放大器（300）还包括电感性退化，使得第一晶体管（301）的源极或发射极连接到第一电感器（321），并且第二晶体管（302）的源极或发射极连接到第二电感器 322）。

5. 发明公开

EP3214759A1 ULTRA-LOW WORKING VOLTAGE RAIL TO RAIL OPERATIONAL AMPLIFIER AND DIFFERENTIAL INPUT AMPLIFICATION-STAGE CIRCUIT AND OUTPUT-STAGE CIRCUIT THEREOF 审中-公开
标题翻译：超低工作电压轨到轨运算放大器和差分输入放大级电路和输出级电路
公开(公告)号：EP3214759A1
公开(公告)日：2017-09-06
申请号：EP15854770.3
申请日：2015-10-27
申请人： Huawei Technologies Co. Ltd.
发明人： TANG, Yangyang , ZHANG, Chenxiong
IPC分类号： H03F3/45
CPC分类号： H03F1/0205 , H03F1/38 , H03F3/45183 , H03F3/45219 , H03F3/45273 , H03F2200/135 , H03F2200/153 , H03F2200/513 , H03F2200/87 , H03F2203/45028 , H03F2203/45036 , H03F2203/45051 , H03F2203/45054 , H03F2203/45114 , H03F2203/45124 , H03F2203/45134 , H03F2203/45221 , H03F2203/45281 , H03F2203/45288 , H03F2203/45342
摘要： A differential input amplification-stage circuit (100) includes a voltage unit (10), first and second bulk-driven transistors (20, 30), first and second mirror current sources (40, 50), and a differential amplifier unit (60). The voltage unit (10) includes first to third voltage output ends (11, 12, 13). The first voltage output end (11) is connected to the first and the second bulk-driven transistors (20, 30); the first and the second bulk-driven transistors (20, 30) respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents; the differential amplifier unit (60) separately outputs first and second adjustment currents under an action of voltages of the first to the third voltage output ends (11, 12, 13); and the first and the second mirror current sources (40, 50) respectively output first and second predetermined currents (I out+ , I out- ) according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit (100). Therefore, output stability is improved. In addition, an output-stage circuit (200) and an ultra-low working voltage rail-to-rail transportation amplified circuit (300) are further provided.
摘要翻译：本发明的差动输入放大级电路（100）包括电压单元（10），第一和第二体驱动晶体管（20,30），第一和第二镜像电流源（40,50）以及差分放大器单元（60 ）。电压单元（10）包括第一至第三电压输出端（11,12,13）。第一电压输出端（11）连接到第一和第二体驱动晶体管（20,30）。第一和第二体驱动晶体管（20,30）分别接收第一和第二输入电压，并且将第一和第二输入电压转换为第一和第二输出电流; 差分放大器单元（60）在第一至第三电压输出端（11,12,13）的电压的作用下分别输出第一和第二调节电流; 并且第一镜像电流源和第二镜像电流源分别根据第一输出电流和第一调节电流以及第二输出电流和第二调节电流输出第一和第二预定电流Iout +，Iout-，以保持差分输入放大级电路（100）的跨导恒定性。因此，输出稳定性得到改善。此外，还提供输出级电路（200）和超低工作电压轨到轨输送放大电路（300）。

6. 发明公开

EP1751853A4 A TUNEABLE CIRCUIT FOR CANCELING THIRD ORDER MODULATION 审中-公开
标题翻译：可调电路匹克第三高阶调制
公开(公告)号：EP1751853A4
公开(公告)日：2009-03-18
申请号：EP05748731
申请日：2005-05-12
申请人： SIRIFIC WIRELESS CORP
发明人： MANKU TAJINDER
IPC分类号： H03F1/32 , H03B1/04 , H03C1/06 , H03D1/02 , H03D7/14 , H03F3/18 , H03F3/45 , H03K5/01 , H03K5/02 , H03K5/1252 , H04B1/04 , H04B1/12 , H04B1/40 , H04B15/06
CPC分类号： H03K5/1252 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03F1/3211 , H03F1/3223 , H03F3/24 , H03F3/45183 , H03F2200/372 , H03F2200/87 , H03F2203/45318 , H03F2203/45366 , H03F2203/45498 , H03F2203/45544 , H03K5/02 , H04B1/0475 , H04B1/123 , H04B2001/0441
摘要： A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.

7. 发明公开

EP0863609A3 Amplifier circuits 失效
标题翻译：放大器电路
公开(公告)号：EP0863609A3
公开(公告)日：2000-02-16
申请号：EP98301602.3
申请日：1998-03-04
申请人： SONY CORPORATION
发明人： Hirabayashi, Atsushi, c/o Sony Corporation , Fujita, Kosuke, c/o Sony Corporation , Komori, Kenji, c/o Sony Corporation , Murayama, Norihiro, c/o Sony Corporation
IPC分类号： H03G1/00
CPC分类号： H03G1/0023 , H03F2200/87 , H03F2203/45468 , H03F2203/45471
摘要： An impedance (2) of a value 2·Z E is connected in series between the emitters of differential pair transistors (1a), (1b) and these emitters are grounded by way of current sources (3a), (3b) respectively. Input signal sources (4a), (4b) of voltage values ±V IN are connected to the bases of the transistors (1a), (1b) by way of the base-emitter paths of transistors (5a), (5b) which form a buffer circuit (10). The emitters of the transistors (5a), (5b) are in turn grounded by way of current sources (6a), (6b) respectively. Further, the collector of each transistor (1a), (1b) is connected to the base of the other transistor (1b), (1a) by way of the base-emitter paths of the transistors (5a), (5b) respectively.

8. 发明公开

EP0863609A2 Amplifier circuits 失效
标题翻译： Verstärkerschaltungen
公开(公告)号：EP0863609A2
公开(公告)日：1998-09-09
申请号：EP98301602.3
申请日：1998-03-04
申请人： SONY CORPORATION
发明人： Hirabayashi, Atsushi, c/o Sony Corporation , Fujita, Kosuke, c/o Sony Corporation , Komori, Kenji, c/o Sony Corporation , Murayama, Norihiro, c/o Sony Corporation
IPC分类号： H03G1/00
CPC分类号： H03G1/0023 , H03F2200/87 , H03F2203/45468 , H03F2203/45471
摘要： An impedance (2) of a value 2·Z E is connected in series between the emitters of differential pair transistors (1a), (1b) and these emitters are grounded by way of current sources (3a), (3b) respectively. Input signal sources (4a), (4b) of voltage values ±V IN are connected to the bases of the transistors (1a), (1b) by way of the base-emitter paths of transistors (5a), (5b) which form a buffer circuit (10). The emitters of the transistors (5a), (5b) are in turn grounded by way of current sources (6a), (6b) respectively. Further, the collector of each transistor (1a), (1b) is connected to the base of the other transistor (1b), (1a) by way of the base-emitter paths of the transistors (5a), (5b) respectively.
摘要翻译：串联在差分对晶体管（1a），（1b）的发射极之间串联连接值为2.ZE的阻抗（2），这些发射极分别通过电流源（3a），（3b）接地。电压值+/- VIN的输入信号源（4a），（4b）通过晶体管（5a），（5b）的基极 - 发射极路径连接到晶体管（1a），（1b）的基极，形成缓冲电路（10）。（5a），（5b）的发射极分别通过电流源（6a），（6b）接地。此外，每个晶体管（1a），（1b）的集电极分别通过晶体管（5a），（5b）的基极 - 发射极连接到另一个晶体管（1b），（1a）的基极。

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