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1. 发明公开

EP4456420A1 METHOD AND APPARATUS FOR INTERFERENCE REDUCTION IN OPTICAL SENSING RECEIVERS 审中-公开
公开(公告)号：EP4456420A1
公开(公告)日：2024-10-30
申请号：EP24170242.2
申请日：2024-04-15
申请人： Avago Technologies International Sales Pte. Limited
发明人： Lu, Junjie , Guo, Jing , Wang, Leon Samuel , Lin, Xiaofeng , Jiang, Xicheng
IPC分类号： H03F3/08 , H03F3/187 , H03F3/45
CPC分类号： H03F3/087 , H03F3/187 , H03F3/45475 , H03F3/45959 , H03F3/45977 , H03F2200/11420130101 , H03F2200/14420130101 , H03F2200/2720130101 , H03F2200/26720130101 , H03F2203/4551220130101 , H03F2203/4552820130101 , H03F2203/4553620130101 , H03F2203/4554420130101
摘要： An apparatus for detecting optical signals includes a photodetector. The photodetector is reverse-biased by a first voltage and a second voltage is added to the first voltage to provide an offset equal to the second voltage for the photodetector. A first circuit is coupled to the first circuit to provide the second voltage for the photodetector and a second circuit is coupled to the first circuit to provide the first voltage to the photodetector to reverse-bias the photodetector. The second circuit provides an output voltage proportional to a current of the photodetector at an output of the second circuit.

2. 发明公开

EP4439979A1 AREA-EFFICIENT COMPENSATION CIRCUIT FOR LOW-POWER MULTI-STAGE AMPLIFIER 审中-公开
公开(公告)号：EP4439979A1
公开(公告)日：2024-10-02
申请号：EP24163199.3
申请日：2024-03-13
申请人： MediaTek Inc.
发明人： CHEN, You-Shin , CHEN, Ya-Chi , WEN, Sung-Han
IPC分类号： H03F1/14 , H03F3/187 , H03F3/21
CPC分类号： H03F3/187 , H03F3/211 , H03F2200/0320130101 , H03F1/14 , H03F2200/13520130101 , H03F2200/15320130101 , H03F2200/29720130101
摘要： The present invention provides a multi-stage amplifier, wherein the multi-stage amplifier includes a plurality of amplifier stages and a compensation circuit. The compensation circuit is coupled to an output terminal of one of the plurality of amplifier stages, and the compensation circuit includes a first auxiliary amplifier, a capacitor, a second auxiliary amplifier, a first resistor and a second resistor. The capacitor is coupled between an input terminal and an output terminal of the first auxiliary amplifier. The second auxiliary amplifier is coupled to the first auxiliary amplifier. The first resistor is coupled between an input terminal and an output terminal of the second auxiliary amplifier. The second resistor is coupled between an output terminal of the first auxiliary amplifier and a ground voltage.

4. 发明公开

EP3407489A1 SWITCHLESS LINE-DI/MIC PRE-AMPLIFIER INPUT 审中-公开
公开(公告)号：EP3407489A1
公开(公告)日：2018-11-28
申请号：EP17202320.2
申请日：2017-11-17
申请人： Tymphany HK Limited
发明人： DE VRIES, Sebastiaan
IPC分类号： H03F3/187 , H03F3/45 , H04R3/00 , H03F3/72 , H03F1/56 , H03F3/68
CPC分类号： H03F3/45475 , H03F1/56 , H03F3/187 , H03F3/68 , H03F2200/03 , H03F2200/222 , H03F2200/261 , H03F2200/42 , H03F2200/48 , H03F2203/7233 , H04R3/00 , H04R2420/09
摘要： A switchless pre-amplifier input circuit includes an audio input connector that receives a first audio device operable at a first impedance and a second audio device operable at a second impedance less than the first impedance. A preamplifier circuit outputs a pre-amplified audio signal in response to amplifying a first audio signal generated by the first audio device or a second audio signal generated by the second audio device. The switchless pre-amplifier input circuit further includes a impedance selector circuit that adjusts an impedance at the output to reach the second impedance in response to connecting the second audio device to the audio input connector and to adjust the impedance at the output to reach the first impedance in response to connecting the first audio device to the audio input.

5. 发明公开

EP3139500A1 MUSIC REPRODUCING DEVICE 审中-公开
标题翻译： MUSIKWIEDERGABEVORRICHTUNG
公开(公告)号：EP3139500A1
公开(公告)日：2017-03-08
申请号：EP16182384.4
申请日：2016-08-02
申请人： Onkyo Corporation
发明人： ASAO, Kei , KAWAGUCHI, Tsuyoshi , YOSHIDA, Makoto , SHIOZAKI, Takanori , NAKANISHI, Yoshinori , ASAHARA, Hiroyuki , KITAGAWA, Norimasa
IPC分类号： H03F3/187 , H03M1/66 , H03F1/02 , H03F3/45 , H03F3/68 , H03F3/72
CPC分类号： H04R5/033 , H03F3/187 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2203/7227 , H03M1/66 , H04R5/04
摘要： Problem: To reduce signal output and wiring to a D/A converter (DAC).
Solution: A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.
摘要翻译：问题：减少D / A转换器（DAC）的信号输出和接线。解决方案：DAP 1包括将LR2将数字音频数据D / A转换成LR 2通道模拟音频数据的DAC7;放大电路9，放大LR2通道模拟音频数据，DAC 7 D / A- 将LR 2通道数字音频数据D / A转换为LR 2通道模拟音频数据的DAC8转换成放大电路10，放大电路10放大反向LR2通道模拟音频数据，LR 2通道模拟音频数据， DAC 8 D / A转换器被反转。

6. 发明授权

EP2884773B1 Public address system and method 有权
标题翻译：音响系统和方法
公开(公告)号：EP2884773B1
公开(公告)日：2017-02-15
申请号：EP13196359.7
申请日：2013-12-10
申请人： Televic Rail NV
发明人： Vercoutter, Bart , Claeys, Luc , Van Den Oudenhoven, Jan , Boerjan, Kristof , Gesquiere, John
IPC分类号： H04R29/00 , H03F3/187 , H03F3/68 , H03F1/52 , H04B1/74
CPC分类号： H04R29/007 , H03F1/526 , H03F3/187 , H03F3/68 , H04R2227/001

7. 发明授权

EP2317644B1 Amplifier activation 有权转让
标题翻译：放大器启动
公开(公告)号：EP2317644B1
公开(公告)日：2015-10-28
申请号：EP09252519.5
申请日：2009-10-30
申请人： ST-Ericsson SA
发明人： Teng, Robert Hwat Hian
IPC分类号： H03F1/30 , H03F1/34 , H03F3/187 , H03F3/45 , H03G3/34
CPC分类号： H03F1/305 , H03F1/342 , H03F3/187 , H03F3/45179 , H03F3/45475 , H03F2200/03 , H03F2200/156 , H03F2200/18 , H03F2200/27 , H03F2200/312 , H03F2200/396 , H03F2200/408 , H03F2200/414 , H03F2200/417 , H03F2200/453 , H03F2200/456 , H03F2200/507 , H03F2200/522 , H03F2203/45101 , H03F2203/45138 , H03F2203/45151 , H03F2203/45171 , H03F2203/45206 , H03F2203/45226 , H03F2203/45528 , H03F2203/45536 , H03F2203/45586 , H03F2203/45588 , H03F2203/45618 , H03F2203/45728 , H03G3/34

8. 发明授权

EP2544344B1 Triple mode charge-pump. 有权
标题翻译：电荷泵有三个模式
公开(公告)号：EP2544344B1
公开(公告)日：2015-05-27
申请号：EP11368021.9
申请日：2011-07-04
申请人： Dialog Semiconductor GmbH
发明人： Brown, Jim
IPC分类号： H02M3/07 , H03F1/02
CPC分类号： H02M3/07 , H02M2003/071 , H02M2003/072 , H03F3/005 , H03F3/187 , H03F2200/03

9. 发明公开

EP2849326A1 Suspend mode in charge pump 审中-公开
标题翻译：待机模式bei einer Ladungspumpe
公开(公告)号：EP2849326A1
公开(公告)日：2015-03-18
申请号：EP13183984.7
申请日：2013-09-11
申请人： ST-Ericsson SA
发明人： Gupta, Sri Ram , Cimaz, Lionel , Somayajula, Shyam
IPC分类号： H02M3/07
CPC分类号： H02M3/07 , H02M2001/0032 , H02M2001/0035 , H03F3/187 , H03F3/45475 , H03F2200/03 , Y02B70/16
摘要： There is described a device comprising:
- a charge pump, CP, with an input and an output, arranged to output a Pulse-Width Modulated, PWM, voltage out of an input voltage coming from a power source, the PWM signal varying between a first voltage and a second voltage,
- a low-pass filter comprising an output capacitor, said output capacitor being arranged to average the PWM voltage and output a given filtered voltage different than the input voltage,

further comprising a controller, arranged to selectively disconnect the CP from the power source, when a load imposed on the filter is under a selected threshold.
摘要翻译：描述了一种装置，包括：具有输入和输出的电荷泵CP被布置成从来自电源的输入电压输出脉宽调制的PWM电压，PWM信号在a 第一电压和第二电压， - 包括输出电容器的低通滤波器，所述输出电容器被布置成平均PWM电压并输出与输入电压不同的给定滤波电压，还包括控制器，所述控制器被布置成选择性地断开当来自滤波器的负载处于选定的阈值以下时，来自电源的CP。

10. 发明公开

EP2781020A1 DIGITAL CLASS-D AMPLIFIER AND DIGITAL SIGNAL PROCESSING METHOD 有权转让
标题翻译： D类数字放大器和方法用于处理数字信号的
公开(公告)号：EP2781020A1
公开(公告)日：2014-09-24
申请号：EP12780732.9
申请日：2012-10-30
申请人： ST-Ericsson SA
发明人： CRIPPA, Carlo , BASSOLI, Rossella
IPC分类号： H03F3/217
CPC分类号： H03F3/185 , H03F3/187 , H03F3/2175 , H03F3/45475 , H03F2200/165 , H03F2200/351 , H03F2200/78 , H03F2203/21112 , H03F2203/21196 , H03K7/08
摘要： A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing a differential output pulse width modulated signal (yn[n],yp[n]).

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