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1. 发明公开

EP0688044A3 III-V Semiconductor structure and method of manufacture 失效
标题翻译： III-V族半导体的结构和它们的制备方法
公开(公告)号：EP0688044A3
公开(公告)日：1997-12-29
申请号：EP95108175
申请日：1995-05-29
申请人： MOTOROLA INC
发明人： CHO JAESHIN , DURLAM MARK , KYLER KELLY W , ABROKWAH JONATHAN K , CRONIN WAYNE A
IPC分类号： H01L21/28 , H01L21/033 , H01L21/283 , H01L21/338 , H01L29/812
CPC分类号： H01L29/66878 , H01L21/0337 , H01L29/812

2. 发明公开

EP0706202A3 Method for producing a pattern and a semiconductor device 失效
标题翻译：制造图案的方法和半导体器件
公开(公告)号：EP0706202A3
公开(公告)日：1996-05-22
申请号：EP95202778.7
申请日：1991-03-19
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Oku, Tomoki, c/o Mitsubishi Denki K.K. Optelec. &
IPC分类号： H01L21/027 , G03F7/20 , H01L21/28 , H01L21/335
CPC分类号： H01L29/66878 , H01L21/0279 , H01L21/266 , H01L21/28587 , H01L21/31058 , H01L29/66462
摘要： A particle beam implantation into a spin-on-glass resin has an effect in hardening the resin of the implanted region. The non-implanted part is not hardened. Therefore, the non-hardened resin of the non-implanted part can be removed with a high selectivity relative to the hardened resin of the implanted part and an inverted pattern comprising hardened resin is produced. The spin-on-glass resin is a silicon compound including a Si-O-CH₃ radical and is convertible upon heating to CH₃, H₂O, and SiO₂
摘要翻译：将粒子束注入旋涂玻璃树脂具有硬化注入区域的树脂的作用。未植入部分未硬化。因此，可以相对于植入部分的硬化树脂以高选择性去除未植入部分的未硬化树脂，并且生成包含硬化树脂的倒转图案。旋涂玻璃树脂是一种含有Si-O-CH 3基团的硅化合物，加热时可转变为CH 3，H 2 O和SiO 2

3. 发明公开

EP0688044A2 III-V Semiconductor structure and method of manufacture 失效
标题翻译： III-V-Halbleiterstruktur und Verfahren zu deren Herstellung
公开(公告)号：EP0688044A2
公开(公告)日：1995-12-20
申请号：EP95108175.1
申请日：1995-05-29
申请人： MOTOROLA, INC.
发明人： Cho, Jaeshin , Durlam, Mark , Kyler, Kelly W. , Abrokwah, Jonathan K. , Cronin, Wayne A.
IPC分类号： H01L21/28 , H01L21/033
CPC分类号： H01L29/66878 , H01L21/0337 , H01L29/812
摘要： A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer (12) is formed on a III-V semiconductor material (10) and a dielectric layer (13) comprised of aluminum is formed on the silicon nitride layer (12). Another dielectric layer (14) comprised of silicon and oxygen is formed over the dielectric layer (13) comprised of aluminum. The dielectric layer (13) comprised of aluminum acts as an etch stop for the etching of the dielectric layer (14) comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer (13) comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer (12). Damage to the surface of the semiconductor material (10) by exposure to the high power reactive ion etch is prevented by forming the dielectric layer (13) comprised of aluminum between the silicon nitride layer (12) and the dielectric layer (14) comprised of silicon and oxygen.
摘要翻译：制造具有小几何形状的可制造的III-V半导体结构。在III-V族半导体材料（10）上形成氮化硅层（12），在氮化硅层（12）上形成由铝构成的电介质层（13）。在由铝组成的电介质层（13）上形成由硅和氧组成的另一介质层（14）。由铝构成的电介质层（13）作为蚀刻停止层，用于蚀刻具有高功率反应离子蚀刻的硅和氧的介电层（14）。然后可以用实质上不蚀刻氮化硅层（12）的湿蚀刻剂来蚀刻由铝构成的电介质层（13）。通过在氮化硅层（12）和介电层（14）之间形成由铝构成的电介质层（13），可以防止暴露于高功率反应离子蚀刻对半导体材料（10）表面的损伤硅和氧。

4. 发明授权

EP0337299B1 A method for manufacturing a field effect transistor 失效
标题翻译：一种制造场效应晶体管的方法。
公开(公告)号：EP0337299B1
公开(公告)日：1995-07-05
申请号：EP89106073.3
申请日：1989-04-06
申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Shikata, Sin-ichi c/o Yokohama Works of
IPC分类号： H01L21/28 , H01L21/00 , H01L21/318
CPC分类号： H01L29/66871 , H01L21/0271 , H01L21/0273 , H01L29/66878

5. 发明公开

EP0598711A2 MESFET source/drain structure 失效
标题翻译： MESFET - 源极/漏极-Struktur。
公开(公告)号：EP0598711A2
公开(公告)日：1994-05-25
申请号：EP94200376.5
申请日：1989-11-29
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Oku, Tomoki, c/o Mitsubishi Denki Kabushiki Kaisha
IPC分类号： H01L29/812 , H01L29/08
CPC分类号： H01L29/66878 , H01L29/0891
摘要： A transistor (fig. 1(i)) having a refractory metal gate (3) on a semi-insulating compound semiconductor substrate (1), asymmetrical side walls (5',7') each side of the gate (3), a low concentration active channel (2) below the gate (3),
source and drain high concentration active regions (8a,8b) each side of the channel (2), and asymmetric intermediate concentration active regions (4a',4b') between source (8a) and channel (2), and channel (2) and drain (8b), respectively, beneath the asymmetrical side walls (5',7'). The side walls (5',7') may be removed.
摘要翻译：在半绝缘化合物半导体衬底（1）上具有难熔金属栅极（3）的晶体管（图1（i）），栅极（3）的每一侧的不对称侧壁（5'，7'），栅极（3）下方的低浓度有源沟道（2），沟道（2）的每一侧的源极和漏极高浓度有源区（8a，8b）和源极（2）之间的不对称中间浓度有源区（4a'，4b'）（8a）和通道（2），通道（2）和排水口（8b）分别位于不对称侧壁（5'，7'）的下方。侧壁（5'，7'）可以被移除。

6. 发明公开

EP0523593A1 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：EP0523593A1
公开(公告)日：1993-01-20
申请号：EP92111907.9
申请日：1992-07-13
申请人： MOTOROLA, INC.
发明人： Cambou, Bertrand F. , Davies, Robert B.
IPC分类号： H01L29/812 , H01L29/10
CPC分类号： H01L29/66878 , H01L21/28587 , H01L21/28593 , H01L29/1029 , H01L29/812
摘要： A semiconductor device having a channel region having a first and a second portion (13a, 13b). The first and second portions of the channel region (13a, 13b) are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.
摘要翻译：一种具有沟道区的半导体器件，该沟道区具有第一和第二部分（13a，13b）。沟道区域（13a，13b）的第一和第二部分被设计成使得在操作期间仅仅一小部分基本耗尽。由此制造具有短栅极长度的半导体器件。

7. 发明公开

EP0498993A3 Field effect transistor and production method therefor 失效
标题翻译：场效应晶体管及其生产方法
公开(公告)号：EP0498993A3
公开(公告)日：1992-10-28
申请号：EP91310880.9
申请日：1991-11-26
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Kohno, Yasutaka, c/o Mitsubishi Denki K. K.
IPC分类号： H01L29/812
CPC分类号： H01L29/66878 , H01L21/314 , H01L29/1029 , H01L29/812
摘要： A field effect transistor comprising a compound semiconductor substrate, a source and a drain electrodes disposed on a compound semiconductor substrate, a gate electrode disposed therebetween, and a layer for reducing the surface levels formed on the surface of the substrate at least between the gate and the drain electrodes. The field effect transistor is produced by a process comprising steps of producing a gate electrode on an active layer which is produced by ion implantation into the semiconductor substrate, producing a source and a drain region by implanting impurity into the entire surface of the substrate using the gate electrode as a mask, producing ohmic electrodes on the source and the drain regions of the substrate, producing a layer for reducing localized surface levels which exists at that region by treating the surface of the substrate at least between the gate and the drain electrodes using predetermined reactive solution or gas, and producing a protecting film on the entire surface of the wafer. Therefor, the field effect transistor having a high gate-drain breakdown voltage is obtained without reducing the yield. This FET can be applied to high output analog integrated circuit.

8. 发明公开

EP0416924A3 Method of producing conductive members on a semiconductor surface 失效
标题翻译：在半导体表面上生产导电成员的方法
公开(公告)号：EP0416924A3
公开(公告)日：1992-03-11
申请号：EP90309770.7
申请日：1990-09-06
申请人： GTE LABORATORIES INCORPORATED
发明人： Lockwood, Harry F. , Tabasky, Marvin , Stern, Margaret B. , Cataldo, Victor
IPC分类号： H01L21/285 , C23C16/04 , H01L29/40
CPC分类号： H01L29/66871 , H01L21/28575 , H01L21/28581 , H01L29/66878
摘要： Method of forming conductive members on a substrate (10 - Fig. 1A) of GaAs. Silicon (13 - Fig. 1B) is placed on the substrate surface (10) in the desired pattern of the conductive members. The substrate (10) is exposed to a gaseous atmosphere containing WF₆. WF₆ is reduced by the silicon causing tungsten to selectively deposit on the silicon but not on the exposed GaAs. The substrate (10) is given a rapid thermal annealing treatment which causes the silicon-tungsten elements (13, 14 - Fig. 1C) to form conductive members (13-14 - Fig. 1D) having a silicon rich layer at the bottom, an intermediate tungsten silicide layer, and a tungsten rich layer at the top. The conductive members form ohmic contacts with underlying heavily doped GaAs and rectifying Schottky barrier contacts with underlying lightly doped GaAs.
摘要翻译：在GaAs衬底（10 - 图1A）上形成导电部件的方法。硅（13-图1B）以导电构件的所需图案放置在衬底表面（10）上。将基板（10）暴露于含有WF6的气氛中。 WF6被硅还原，导致钨选择性地沉积在硅上而不暴露在GaAs上。衬底（10）被给予快速热退火处理，其使得硅 - 钨元件（13,14-图1C）形成底部具有富硅层的导电构件（13-14-图1D）中间硅化钨层和顶部富钨层。导电构件与下面的重掺杂GaAs和整流肖特基势垒接触与下面的轻掺杂GaAs形成欧姆接触。

9. 发明公开

EP0467636A1 Method of manufacturing field effect transistors 失效
标题翻译： Verfahren zur Herstellung von Feldeffekttransistoren。
公开(公告)号：EP0467636A1
公开(公告)日：1992-01-22
申请号：EP91306428.3
申请日：1991-07-16
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Fujii, Takayuki, c/o Mitsubishi Denki K.K. , Nakatani, Mitsunori, c/o Mitsubishi Denki K.K.
IPC分类号： H01L21/338 , H01L21/28
CPC分类号： H01L29/66878 , H01L29/1075 , H01L29/42316
摘要： A method of producing a field effect transistor includes forming a first conductivity type active layer having a first concentration of dopant impurities producing the first conductivity type in a semi-insulating semiconductor substrate, forming a mask film on the substrate on part of the first conductivity type region, depositing a gate metal film on the mask film and on the substrate not covered by the mask film, etching the gate metal film and leaving a portion of the gate metal film on the substrate adjacent to and contacting the mask film as a gate electrode, implanting dopant impurities producing a second conductivity type in the substrate using the mask film and the gate electrode as an implantation mask, annealing the substrate at an elevated temperature to activate the implanted dopant impurities whereby some of the implanted dopant impurities diffuse laterally within the substrate to produce a second conductivity type region in the substrate underneath part of the gate electrode, removing the mask film, implanting dopant impurities producing the first conductivity type in the substrate using the gate electrode as an ion implantation mask to produce first and second doped regions in the substrate on opposite sides of the gate electrode and having a second concentration of dopant impurities larger than the first concentration, the second doped region being disposed within the second conductivity type region that extends underneath part of the gate electrode, and forming a source electrode on the first doped region and a drain electrode on the second doped region.
摘要翻译：一种制作场效应晶体管的方法包括在半绝缘半导体衬底中形成具有产生第一导电类型的掺杂剂杂质的第一浓度的第一导电型有源层，在第一导电类型的一部分上形成掩模膜在掩模膜上和未被掩模膜覆盖的衬底上沉积栅极金属膜，蚀刻栅极金属膜并将栅极金属膜的一部分留在基板上，作为栅电极与掩模膜相邻并接触使用掩模膜和栅电极作为注入掩模在衬底中注入产生第二导电类型的掺杂杂质，在升高的温度下退火衬底以激活注入的掺杂杂质，由此一些注入的掺杂杂质在衬底内横向扩散以在栅极电极的一部分下方的衬底中产生第二导电类型区域去除掩模膜，使用栅电极作为离子注入掩模将产生第一导电类型的掺杂剂杂质注入到衬底中，以在栅电极的相对侧上的衬底中产生第一和第二掺杂区域，并且具有第二浓度掺杂杂质大于第一浓度，第二掺杂区域设置在第二导电类型区域内，延伸在栅电极的一部分下方，以及在第一掺杂区上形成源电极，在第二掺杂区上形成漏电极。

10. 发明公开

EP0392120A1 Semiconductor device with a gate having asymmetric sidewalls, and a production method thereof 失效
标题翻译：使用非对称的侧壁，以及它们的制备方法的半导体器件。
公开(公告)号：EP0392120A1
公开(公告)日：1990-10-17
申请号：EP89312417.2
申请日：1989-11-29
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Oku, Tomoki Mitsubishi Denki K. K. Optelectronic
IPC分类号： H01L29/60 , H01L29/812 , H01L21/28 , H01L29/10
CPC分类号： H01L29/66878 , H01L29/0891
摘要： A production method of a semiconductor device constituting a Schottky barrier gate type field effect transistor includes the steps of producing a low concentration active region at a desired position of a semi-insulating compound semiconductor substrate and producing a gate electrode comprising refractory metal on the active region, producing a first insulating film and etching the same thereby to produce first side wall assist films comprising the first insulating film at the both side walls of the gate electrode, removing one of the first side wall assist films at the side where a source electrode is to be produced by wet etching, plating a second insulating film to the thickness less than that of the first insulating film, etching the second insulating film thereby to produce a second side wall assist film having narrower width than that of the first side wall assist film at the side wall of the gate electrode at the side where the source electrode is to be produced, and conducting ion implantation with using the first and second side wall assist films and the gate electrode as a mask thereby to produce high concentration active regions in asymmetrical configurations at left and right at the both sides of the gate electrode.
摘要翻译：的半导体装置的构成的肖特基势垒栅型场效应晶体管的制造方法包括：在半绝缘化合物半导体衬底的所希望的位置产生一个低浓度活性区域并产生一栅电极上的有源区，其包括难熔金属的步骤，产生第一绝缘膜和蚀刻从而相同的，以产生第一侧壁辅助膜包括第一绝缘电影在栅电极的侧壁bothside，去除所述第一侧壁中的一个在其中源电极侧辅助膜通过湿法蚀刻来制造，电镀的第二绝缘膜的厚度小于所述第一绝缘膜，电影，蚀刻第二绝缘膜，从而产生第二侧壁辅助具有膜窄的宽度比第一侧壁的的辅助成膜在在一侧的栅电极的侧壁，其中所述源电极将被产生，并且导电离子注入使用所述第一和第二侧壁辅助膜和栅电极作为掩模，从而在栅电极的bothsides产生在左右不对称配置高浓度的有源区。

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