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    • 3. 发明公开
    • VERSTÄRKERSCHALTUNG
    • EP1861919A1
    • 2007-12-05
    • EP06723489.8
    • 2006-03-17
    • ATMEL Germany GmbH
    • BROMBERGER, Christoph
    • H03F1/22H03F1/32H03F3/195H01L27/082
    • H03F1/22H01L27/0744H01L27/0823H03F1/32H03F3/195H03F2200/18
    • The invention relates to an amplifier circuit for amplifying an input signal (iEIN) with a vertically integrated cascode (10). Said cascode comprises: a collector semiconductor region (1) of a collector (C), a first base semiconductor region (2) pertaining to a first base (B1) and adjacent to the collector semiconductor region (1), a second base semiconductor region (4) pertaining to a second base (B2), an intermediate base semiconductor region (3) which is adjacent to both the first base semiconductor region (2) and the second base semiconductor region (4), and an emitter semiconductor region (5) pertaining to an emitter (E) and adjacent to the second base semiconductor region (4). According to the invention, a signal input (EIN) is connected to the second base (B2) and the first base (Bl) is connected to the second base by means of a network (NW) in such a way that a small signal voltage (UBl) on the first base (Bl) is coupled to a small signal voltage (Ub2) on the second base (B2) and/or a small signal current (iB2) is coupled through the second base (B2).
    • 本发明涉及用垂直集成共源共栅(10)放大输入信号(iEIN)的放大器电路。 所述共源共栅包括:集电极(C)的集电极半导体区(1),属于第一基极(B1)且与集电极半导体区(1)相邻的第一基极半导体区(2),第二基极半导体区 (2),与第一基础半导体区(2)和第二基础半导体区(4)两者相邻的中间基础半导体区(3),以及发射极半导体区(5) )属于发射极(E)并与第二基础半导体区(4)相邻。 根据本发明,信号输入(EIN)连接到第二基座(B2),并且第一基座(B1)通过网络(NW)连接到第二基座,使得小信号电压 (B1)上的第一基极(UB1)耦合到第二基极(B2)上的小信号电压(Ub2)和/或通过第二基极(B2)耦合小信号电流(iB2)。
    • 4. 发明公开
    • A method in the fabrication of an integrated injection logic circuit
    • Verfahren zur Herstellung einer integrierten Injektions-Logikschaltung
    • EP1646084A1
    • 2006-04-12
    • EP04023839.6
    • 2004-10-06
    • Infineon Technologies AG
    • Johansson, TedNorström, Hans
    • H01L21/8226H01L27/02
    • H01L21/8226H01L21/8224H01L27/0214H01L27/0237H01L27/0744H01L27/0821H01L29/6625H01L29/735
    • A method in the fabrication of an I 2 L circuit comprises (i) forming a common base of a lateral bipolar transistor and emitter of a vertical bipolar multicollector transistor, a common collector of the lateral transistor and base of the vertical multicollector transistor, and an emitter (10) of the lateral transistor in a substrate; (ii) forming, from a first deposited polycrystalline layer, a contact region (7') for the common collector/base and a contact region (7'') for the emitter of the lateral transistor; (iii) forming an isolation structure (8) for electric isolation of the polycrystalline contact region (7') for the common collector/base; and (iv) forming, from a second deposited polycrystalline layer, a contact region (11') for the common base/emitter and multiple collectors (11'') of the vertical multicollector transistor.
    • 制造I 2 L电路的方法包括:(i)形成横向双极晶体管和垂直双极多晶体管晶体管的发射极,垂直多晶体管的横向晶体管和基极的公共集电极的公共基极,以及 发射极(10); (ii)从第一沉积多晶层形成用于公共集电极/基极的接触区域(7')和用于横向晶体管的发射极的接触区域(7“); (iii)形成用于电绝缘用于共用集电极/基极的多晶接触区域(7')的隔离结构(8) 和(iv)从第二沉积的多晶层形成用于所述垂直多聚电晶体管的公共基极/发射极和多个集电极(11“)的接触区域(11')。