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    • 2. 发明公开
    • LOW CAPACITANCE SCR WITH TRIGGER ELEMENT
    • 较差的可控硅触发要素能力
    • EP1946381A2
    • 2008-07-23
    • EP06816769.1
    • 2006-10-11
    • Texas Instruments Incorporated
    • BOSELLI, Gianluca
    • H01L29/74
    • H01L29/87H01L27/0262H01L27/0817H01L29/66121H03K17/0403H03K17/08108
    • A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element (522). A first well region (504) of a first conductivity type formed within a semiconductor body (502). A first region (510) of the first conductivity type is formed within the first well region. A second region (512) of a second conductivity type is formed with the first well region. A second well region (506) having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region (514) of the first conductivity type is formed within the second well region. A fourth region (516) of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad (518) is connected to the second region. A second terminal (520) is connected to the third region, the fourth region, and the trigger element. In operation, the first terminal conducts current to the second terminal during a low impedance state in response to the altered trigger voltage being applied to the first terminal.
    • 3. 发明公开
    • Static induction thyristor
    • Statischer Induktion可控硅
    • EP0559133A1
    • 1993-09-08
    • EP93103283.3
    • 1993-03-02
    • ZAIDAN HOJIN HANDOTAI KENKYU SHINKOKAI
    • Nishizawa, Jun-ichi
    • H01L29/72
    • H01L27/0817H01L29/7392
    • A static induction device (SI device) at least shares a structure in which an SI thyristor, an IGT and a capacitor are merged onto the single monolithic chip. The SI thyristor has a cathode (23), an anode (21) and gate regions (31), and a channel (22). The IGT has a well (59) on a surface of the channel, a source (31) and drain (32) regions within the well, a gate insulating film on the well, and a gate electrode (25) on the gate insulating film. The capacitor comprises the gate region (31) of the SI thyristor, the gate insulating film on the gate region, and the gate electrode (25). The cathode and the drain region are connected to each other through a high-conductive electrode (231).
    • 静态感应装置(SI装置)至少共享将SI晶闸管,IGT和电容器合并到单片芯片上的结构。 SI晶闸管具有阴极(23),阳极(21)和栅极区域(31)以及通道(22)。 IGT在通道的表面上具有阱(59),阱内的源极(31)和漏极(32)区域,阱上的栅极绝缘膜以及栅极绝缘膜上的栅电极(25) 。 电容器包括SI晶闸管的栅极区域(31),栅极区域上的栅极绝缘膜和栅电极(25)。 阴极和漏极区域通过高导电电极(231)彼此连接。
    • 8. 发明公开
    • LOW CAPACITANCE SCR WITH TRIGGER ELEMENT
    • KAPAZITÄTSARMERSCR MIT TRIGGERELEMENT
    • EP1946381A4
    • 2008-12-10
    • EP06816769
    • 2006-10-11
    • TEXAS INSTRUMENTS INC
    • BOSELLI GIANLUCA
    • H01L29/87H01L21/329H01L27/02H01L29/06H01L29/74H03K17/00
    • H01L29/87H01L27/0262H01L27/0817H01L29/66121H03K17/0403H03K17/08108
    • A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity type formed within a semiconductor body. A first region of the first conductivity type is formed within the first well region. A second region of a second conductivity type is formed with the first well region. A second well region having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region of the first conductivity type is formed within the second well region. A fourth region of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad is connected to the second region. A second terminal is connected to the third region, the fourth region, and the trigger element. In operation, the first terminal conducts current to the second terminal during a low impedance state in response to the altered trigger voltage being applied to the first terminal.
    • 具有可选触发和保持电压的硅整流器半导体器件包括触发元件(522)。 形成在半导体主体(502)内的第一导电类型的第一阱区(504)。 第一导电类型的第一区域(510)形成在第一阱区域内。 第二导电类型的第二区域(512)与第一阱区域一起形成。 具有第二导电类型的第二阱区(506)形成在与第一阱区相邻的半导体本体内。 第一导电类型的第三区域(514)形成在第二阱区域内。 第二导电类型的第四区域(516)形成在第二阱区内。 触发元件连接到第一区域并且将基极触发电压和基极保持电压改变成改变的触发电压和改变的保持电压。 第一端子或垫(518)连接到第二区域。 第二端子(520)连接到第三区域,第四区域和触发元件。 在操作中,响应于改变的触发电压被施加到第一端子,第一端子在低阻抗状态期间将电流传导到第二端子。