专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

2. 发明公开

EP2847786A1 VERFAHREN ZUM BONDEN VON SUBSTRATEN 有权
标题翻译： VERFAHREN ZUM BONDEN VON基板
公开(公告)号：EP2847786A1
公开(公告)日：2015-03-18
申请号：EP12742878.7
申请日：2012-07-26
申请人： Ev Group E. Thallner GmbH
发明人： WIMPLINGER, Markus
IPC分类号： H01L21/60
CPC分类号： H01L24/83 , B32B37/24 , B32B38/0008 , B32B2037/243 , B32B2037/246 , B32B2457/14 , C23C14/08 , C23C14/081 , C23C14/086 , C23C16/40 , C23C16/403 , C23C16/407 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/75 , H01L31/18 , H01L2224/2741 , H01L2224/27418 , H01L2224/2745 , H01L2224/27452 , H01L2224/278 , H01L2224/27848 , H01L2224/2908 , H01L2224/29187 , H01L2224/29287 , H01L2224/29394 , H01L2224/29395 , H01L2224/3201 , H01L2224/32145 , H01L2224/32501 , H01L2224/7501 , H01L2224/75101 , H01L2224/83001 , H01L2224/83002 , H01L2224/83011 , H01L2224/83012 , H01L2224/83013 , H01L2224/83065 , H01L2224/83075 , H01L2224/8322 , H01L2224/8383 , H01L2224/83896 , H01L2224/83907 , H01L2924/01009 , H01L2924/01013 , H01L2924/0103 , H01L2924/01031 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/053 , H01L2924/12042 , H01L2924/20102 , H01L2924/0549 , H01L2924/00014 , H01L2924/00012 , H01L2924/0531 , H01L2924/01001 , H01L2924/01008 , H01L2924/00
摘要： The present invention relates to a method for bonding a first contact area (3) of a first, at least predominantly transparent substrate (1) to a second contact area (4) of a second, at least predominantly transparent substrate (2) wherein an oxide is used at at least one of the contact areas for bonding, from which oxide an at least predominantly transparent connecting layer (14) having: an electrical conductivity of at least 10e1 S/cm
2 (measurement: four-point method, relative to temperature of 300K) and an optical transmittance of greater than 0.8 (for a wavelength range of 400 nm to 1500 nm) is formed at the first and second contact areas (3 4).
摘要翻译：本发明涉及一种用于将第一至少大部分透明的基板的第一接触区域与第二至少大部分透明的基板的第二接触区域接合在至少一个接触区域上的方法，所述接触区域是用于接合的氧化物，形成至少大体上透明的互连层，其电导率为至少10e1S / cm 2（测量：四点法，相对于温度为300K），光透射率大于0.8（波长范围为400nm 至1500nm）在第一和第二接触区域上。

3. 发明公开

EP0444820A2 MMIC package and connection 失效
标题翻译： MMIC-Gehäuseund Anschluss。
公开(公告)号：EP0444820A2
公开(公告)日：1991-09-04
申请号：EP91301354.6
申请日：1991-02-20
申请人： RAYTHEON COMPANY
发明人： Lehman, George R. , Miller, Steven W. , Bilski, Stacey M.
IPC分类号： H01L23/66 , H01L23/04 , H01L25/07
CPC分类号： H01L23/66 , H01L2224/45144 , H01L2224/75101 , H01L2224/81091 , H01L2224/81193 , H01L2224/81209 , H01L2224/8182 , H01L2924/16152 , H01L2924/3011 , H01L2924/00
摘要： A package for electronic components, especially MMIC components, is constructed from layers (12,14,16,18,20)) of ceramic cofired to form an annular piece. Metal pieces (10,22,24) are brazed onto the top and bottom of the annular piece to hermetically seal the package. Certain of the ceramic pieces (12,14,16,18,20) are coated with patterns of conductive material before cofiring. The conductive material forms DC power distribution lines (32A, 32B) to electronic components (28A, 28B) within the package and low loss RF feedthroughs (50A, 50B) into the package.
摘要翻译：用于电子部件，特别是MMIC部件的包装由共同燃烧以形成环形件的陶瓷层（12,14,16,18,20）构成。将金属片（10,22,24）钎焊到环形片的顶部和底部上以气密地密封包装。某些陶瓷片（12,14,16,18,20）在共烧之前涂覆有导电材料的图案。导电材料形成到封装内的电子部件（28A，28B）和低损耗RF馈通（50A，50B）的直流配电线（32A，32B）。

4. 发明公开

EP3098837A3 DIE BONDING APPARATUS COMPRISING THREE INERT GAS CONTAINERS 有权转让
标题翻译： TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER
公开(公告)号：EP3098837A3
公开(公告)日：2017-02-08
申请号：EP16001177.1
申请日：2016-05-24
申请人： ASM Technology Singapore Pte Ltd.
发明人： LAU, Siu Wing , HUNG, Kin Yik , AU, Yuk Cheung , LAI, Wing Chiu , LEE, Man Leo , GO, Sai Yuen
IPC分类号： H01L21/67 , H01L21/603
CPC分类号： H01L24/75 , H01L21/67742 , H01L24/81 , H01L2224/7501 , H01L2224/751 , H01L2224/75101 , H01L2224/75251 , H01L2224/75252 , H01L2224/75305 , H01L2224/7565 , H01L2224/75804 , H01L2224/75821 , H01L2224/75824 , H01L2224/75841 , H01L2224/759 , H01L2224/81011 , H01L2224/81022 , H01L2224/81024 , H01L2224/81075 , H01L2224/81093 , H01L2224/81203 , H01L2924/00012
摘要： A die bonding apparatus (10) comprises a first inert gas container (40) having a first inert gas concentration and a second inert gas container (50) having a second inert gas concentration enclosed within the first inert gas container (40). The second inert gas concentration is higher than the first inert gas concentration. The die bonding apparatus (10) further comprises a bond head (52) located in the second inert gas container (50) for receiving a die (24) for bonding and a third inert gas container (80) having an inert gas environment that is separate from the first and second inert gas containers (40, 50) and where a substrate (26) is locatable for die bonding. The bond head (52) is operative to move the die (24) between a first position within the second inert gas container (50) and a second position within the third inert gas container (80) to bond the die (24) onto the substrate (26) located in the third inert gas container (80). The third inert gas container (80) may comprise a portion of a bond stage (60) enclosed by the walls (62) on the sides, by a bond stage pedestal (66) on the bottom and by the first inert gas container (40) base plate (42) on the top. The bond stage (60) is movable for receiving the substrate (26) to be processed and below the first inert gas container (40). The bond stage walls (62) may comprise a plurality of inert gas outlets (64, 68, 69) for expelling inert gas towards the first inert gas container (40) to form an air curtain to restrict ambient air from entering the third inert gas container (80).
摘要翻译：芯片接合装置（10）包括具有第一惰性气体浓度的第一惰性气体容器（40）和封闭在第一惰性气体容器（40）内的第二惰性气体浓度的第二惰性气体容器（50）。第二惰性气体浓度高于第一惰性气体浓度。芯片接合装置（10）还包括位于第二惰性气体容器（50）中的用于接收用于接合的模具（24）的接合头（52）和具有惰性气体环境的第三惰性气体容器（80）与第一和第二惰性气体容器（40,50）分离，并且其中基板（26）可定位用于管芯接合。接合头（52）可操作以使模具（24）在第二惰性气体容器（50）内的第一位置和第三惰性气体容器（80）内的第二位置之间移动，以将模具（24）接合到基板（26）位于第三惰性气体容器（80）中。第三惰性气体容器（80）可以包括由侧壁上的壁（62）包围的结合台（60）的一部分，底部上的结合台基座（66）和第一惰性气体容器（40））底板（42）。接合台（60）可移动以接收待处理的基板（26）并在第一惰性气体容器（40）的下方。结合阶段壁（62）可以包括多个惰性气体出口（64,68,69），用于朝向第一惰性气体容器（40）排出惰性气体，以形成空气幕，以限制环境空气进入第三惰性气体容器（80）。

5. 发明公开

EP2843692A1 SEMICONDUCTOR DEVICE FABRICATION METHOD, THERMALLY INSULATED LOAD JIG, AND THERMALLY INSULATED LOAD JIG MOUNTING METHOD 审中-公开
标题翻译：法半导体元件，隔热LOAD SPAN设备及其安装方法隔热LOAD JIG
公开(公告)号：EP2843692A1
公开(公告)日：2015-03-04
申请号：EP13782144.3
申请日：2013-04-24
申请人： Nissan Motor Co., Ltd
发明人： TANIMOTO, Satoshi , ZUSHI, Yusuke , MURAKAMI, Yoshinori , MATSUI, Kohei , SATO, Shinji , FUKUSHIMA, Yu
IPC分类号： H01L21/52 , H05K13/04
CPC分类号： H01L24/83 , B23K37/0426 , H01L24/05 , H01L24/29 , H01L24/75 , H01L24/97 , H01L2224/04026 , H01L2224/05082 , H01L2224/05155 , H01L2224/05166 , H01L2224/05639 , H01L2224/2732 , H01L2224/291 , H01L2224/29118 , H01L2224/29144 , H01L2224/75101 , H01L2224/75305 , H01L2224/7531 , H01L2224/75314 , H01L2224/75315 , H01L2224/75317 , H01L2224/7532 , H01L2224/75756 , H01L2224/7598 , H01L2224/75981 , H01L2224/83022 , H01L2224/83048 , H01L2224/83075 , H01L2224/83101 , H01L2224/832 , H01L2224/83211 , H01L2224/83444 , H01L2224/83447 , H01L2224/83801 , H01L2224/83815 , H01L2224/97 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/10254 , H01L2924/10272 , H01L2924/1033 , H01L2924/1037 , H01L2924/1067 , H01L2924/12032 , H01L2924/12036 , H01L2924/13062 , H01L2924/13091 , H01L2924/15724 , H01L2924/15747 , H01L2924/15787 , H01L2924/3656 , H05K3/34 , H05K3/3431 , H05K13/0465 , H05K2203/0195 , H05K2203/0278 , H01L2924/00 , H01L2924/0542 , H01L2924/0103 , H01L2924/00014 , H01L2924/01042 , H01L2924/01032 , H01L2924/01014 , H01L2924/01013 , H01L2224/05655 , H01L2224/83 , H01L2924/00012
摘要： In a heat insulating load jig 11 of the present invention, a solder material 14 having a melting point or a solidus temperature in a range between a thermal resistance temperature of a semiconductor chip 13 and a temperature 100°C below the thermal resistance temperature is interposed between a circuit board 12 and the semiconductor chip 13; a heat insulating body 17 is placed on an upper side of the semiconductor chip 13 in this state; a metal weight 16 is disposed on the heat insulating body 17; and load is applied to the semiconductor chip 13 while the solder material 14 is melted and solidified.
摘要翻译：在本发明中，具有在半导体芯片13的热电阻温度和温度100℃以下的热电阻温度之间的范围内的熔点或固相线温度的焊料材料14的热绝缘负荷夹具11夹一电路板12和半导体芯片13之间; 隔热体17在这种状态下，半导体芯片13的上侧被置于; 金属重物16设置在绝热体17; 并且在焊接材料14被熔融固化负载被施加到半导体芯片13。

6. 发明公开

EP3061125A1 FOCAL PLANE ARRAY PACKAGING USING ISOSTATIC PRESSURE PROCESSING 有权
标题翻译： WITH等静压处理焦平面阵列ENCAPSULATION
公开(公告)号：EP3061125A1
公开(公告)日：2016-08-31
申请号：EP14793344.4
申请日：2014-10-01
申请人： Raytheon Company
发明人： GERBER, Kenneth, Allen , GETTY, Jonathan , RAMIREZ, Aaron, M. , MILLER, Scott, S.
IPC分类号： H01L21/603 , H01L21/67 , H01L27/146
CPC分类号： H01L31/0203 , H01L24/26 , H01L24/75 , H01L24/81 , H01L24/83 , H01L27/144 , H01L27/14634 , H01L27/1465 , H01L27/1469 , H01L2224/16145 , H01L2224/75101 , H01L2224/81193 , H01L2224/81209 , H01L2224/8182 , H01L2924/351
摘要： A method for bonding a first semiconductor body (10) having a plurality of electromagnetic radiation detectors to a second semiconductor body (14) having read out integrated circuits for the detectors. The method includes: aligning electrical contacts (17) for the plurality of electromagnetic radiation detectors with electrical contacts (18) of the read out integrated circuits; tacking the aligned electrical contacts for the plurality of electromagnetic radiation detectors with electrical contacts of the read out integrated circuits to form an intermediate stage structure; packaging the intermediate stage structure into a vacuum sealed electrostatic shielding container (22) having flexible walls; inserting the package with the intermediate stage structure therein into an isostatic pressure chamber (24); and applying the isostatic pressure to the intermediate stage structure through walls of the container. The container includes a stand-off to space walls of the container from edges of the first semiconductor body.

7. 发明公开

EP2587900A1 JOINT STRUCTURE MANUFACTURING METHOD, HEATING AND MELTING TREATMENT METHOD, AND SYSTEM FOR SAME 有权
标题翻译：维也纳国家公民权利与政治权利国际公约“，”维也纳公民权利和政治权利国际公约“
公开(公告)号：EP2587900A1
公开(公告)日：2013-05-01
申请号：EP11800738.4
申请日：2011-06-24
申请人： Ayumi Industry Co., Ltd.
发明人： ABE, Hideyuki , MAWATARI, Kazuaki
IPC分类号： H05K3/34 , B23K1/00 , B23K1/008 , B23K31/02 , H01L21/60 , B23K101/40 , B23K101/42
CPC分类号： B23K3/0607 , B23K1/0016 , B23K1/008 , B23K1/20 , B23K1/206 , B23K3/04 , B23K3/082 , B23K31/02 , B23K35/38 , B23K2101/40 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13155 , H01L2224/13164 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/75101 , H01L2224/7515 , H01L2224/75272 , H01L2224/81002 , H01L2224/81011 , H01L2224/81014 , H01L2224/81019 , H01L2224/81054 , H01L2224/8109 , H01L2224/81193 , H01L2224/81211 , H01L2224/81805 , H01L2224/81815 , H01L2224/81907 , H01L2224/83104 , H01L2924/01322 , H05K3/305 , H05K3/3436 , H05K13/0465 , H05K2203/083 , H05K2203/085 , H05K2203/087 , Y02P70/613 , H01L2924/00012 , H01L2924/00014 , H01L2924/0105 , H01L2924/01047 , H01L2924/00
摘要： A soldering method capable of alleviating positional displacement between substrates even though a step of removing flux can be omitted is provided.
A temporary bonding agent 55 is applied onto multiple substrates 50a, 50b, and a heater 33 heats the substrates while the substrates are temporarily bonded with the temporary bonding agent 55 interposed therebetween, and before the solder 54 is melted or while the solder 54 is melted, the temporary bonding agent 55 is evaporated, and the substrates 50a, 50b are bonded with solder with the melted solder 54 interposed therebetween.
摘要翻译：提供了能够减轻基板之间的位置偏移的焊接方法，即使可以省略去除焊剂的步骤。临时粘合剂55被施加到多个基板50a，50b上，并且加热器33加热基板，同时基板临时粘合在其间插入临时粘合剂55，并且在焊料54熔化之前或焊料54熔化之前，临时粘合剂55蒸发，并且基板50a，50b与焊料接合，熔融的焊料54插入其间。

9. 发明公开

EP2843692A4 SEMICONDUCTOR DEVICE FABRICATION METHOD, THERMALLY INSULATED LOAD JIG, AND THERMALLY INSULATED LOAD JIG MOUNTING METHOD 审中-公开
标题翻译：法半导体元件，隔热LOAD SPAN设备及其安装方法隔热LOAD JIG
公开(公告)号：EP2843692A4
公开(公告)日：2016-03-09
申请号：EP13782144
申请日：2013-04-24
申请人： NISSAN MOTOR
发明人： TANIMOTO SATOSHI , ZUSHI YUSUKE , MURAKAMI YOSHINORI , MATSUI KOHEI , SATO SHINJI , FUKUSHIMA YU
IPC分类号： H01L21/67 , H01L21/60 , H01L21/68
CPC分类号： H01L24/83 , B23K37/0426 , H01L24/05 , H01L24/29 , H01L24/75 , H01L24/97 , H01L2224/04026 , H01L2224/05082 , H01L2224/05155 , H01L2224/05166 , H01L2224/05639 , H01L2224/2732 , H01L2224/291 , H01L2224/29118 , H01L2224/29144 , H01L2224/75101 , H01L2224/75305 , H01L2224/7531 , H01L2224/75314 , H01L2224/75315 , H01L2224/75317 , H01L2224/7532 , H01L2224/75756 , H01L2224/7598 , H01L2224/75981 , H01L2224/83022 , H01L2224/83048 , H01L2224/83075 , H01L2224/83101 , H01L2224/832 , H01L2224/83211 , H01L2224/83444 , H01L2224/83447 , H01L2224/83801 , H01L2224/83815 , H01L2224/97 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/10254 , H01L2924/10272 , H01L2924/1033 , H01L2924/1037 , H01L2924/1067 , H01L2924/12032 , H01L2924/12036 , H01L2924/13062 , H01L2924/13091 , H01L2924/15724 , H01L2924/15747 , H01L2924/15787 , H01L2924/3656 , H05K3/34 , H05K3/3431 , H05K13/0465 , H05K2203/0195 , H05K2203/0278 , H01L2924/00 , H01L2924/0542 , H01L2924/0103 , H01L2924/00014 , H01L2924/01042 , H01L2924/01032 , H01L2924/01014 , H01L2924/01013 , H01L2224/05655 , H01L2224/83 , H01L2924/00012
摘要： In a heat insulating load jig 11 of the present invention, a solder material 14 having a melting point or a solidus temperature in a range between a thermal resistance temperature of a semiconductor chip 13 and a temperature 100°C below the thermal resistance temperature is interposed between a circuit board 12 and the semiconductor chip 13; a heat insulating body 17 is placed on an upper side of the semiconductor chip 13 in this state; a metal weight 16 is disposed on the heat insulating body 17; and load is applied to the semiconductor chip 13 while the solder material 14 is melted and solidified.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式