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1. 发明公开

EP2847787A1 ZWEISTUFIGES VERFAHREN ZUM FÜGEN EINES HALBLEITERS AUF EIN SUBSTRAT MIT VERBINDUNGSMATERIAL AUF SILBERBASIS 审中-公开
标题翻译：两阶段的过程，用于向衬底，相关材料在银基半导体的接合
公开(公告)号：EP2847787A1
公开(公告)日：2015-03-18
申请号：EP13715652.7
申请日：2013-04-02
申请人： Robert Bosch GmbH
发明人： FRUEH, Christiane , GUENTHER, Michael , HERBOTH, Thomas
IPC分类号： H01L21/60
CPC分类号： H01L24/83 , H01L24/27 , H01L24/29 , H01L24/32 , H01L2224/2731 , H01L2224/2732 , H01L2224/27442 , H01L2224/27505 , H01L2224/27901 , H01L2224/29082 , H01L2224/29083 , H01L2224/29339 , H01L2224/32225 , H01L2224/75315 , H01L2224/831 , H01L2224/83192 , H01L2224/83203 , H01L2224/83208 , H01L2224/8384 , H01L2924/01047 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/15747 , H01L2924/201 , H01L2924/20101 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/2011 , H01L2924/20111 , H01L2924/00
摘要： The invention relates to a method for joining a semiconductor (20) to a substrate (10), comprising the following steps: • applying a first paste layer (1) of a sintering paste to the substrate; • heating and compressing the first paste layer to form a first sintered layer; • applying a second paste layer (2) of a sintering paste to the first sintered layer and arranging a semiconductor (20) on the second paste layer; • heating and compressing the second paste layer (2) to form a second sintered layer. The invention further relates to a semiconductor component produced by means of the method.

2. 发明公开

EP2693465A1 Electronic device and method of manufacturing such device 审中-公开
标题翻译： Elektronische Vorrichtung Verfahren zur Herstellung solch einer Vorrichtung
公开(公告)号：EP2693465A1
公开(公告)日：2014-02-05
申请号：EP12178628.9
申请日：2012-07-31
申请人： NXP B.V.
发明人： Rijckevorsel, Johannes Wilhelmus , Dijkstra, Paul , De Langen, Michel , Bruin, Emiel
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/27502 , H01L2224/27848 , H01L2224/27901 , H01L2224/29144 , H01L2224/32245 , H01L2224/83191 , H01L2224/83439 , H01L2224/83444 , H01L2224/83805 , H01L2924/0132 , H01L2924/01322 , H01L2924/10253 , H01L2924/1203 , H01L2924/1301 , H01L2924/1304 , H01L2924/15747 , H01L2924/01014 , H01L2924/00014 , H01L2924/20109 , H01L2924/2011 , H01L2924/01032 , H01L2924/01079
摘要： The invention relates to a method of manufacturing a semiconductor device (1'). The method comprises steps of: i) providing a semiconductor chip (10') comprising a silicon layer (11) at a side thereof, and further comprising a first attachment layer (13) directly on the silicon layer (11), wherein the first attachment layer (13) comprises gold; ii) heating the semiconductor chip (10') to above a predefined temperature forming an alloy layer (13') comprising gold-silicon alloy; iii) providing a second attachment layer (14) directly on the alloy layer (13'), wherein the second attachment layer (14) comprises gold; iv) providing a conductive substrate (200) for receiving the semiconductor chip (10'); v) providing the semiconductor chip (10') on a surface of the conductive substrate (200); vi) heating the assembly to a further predefined temperature above a melting point of the alloy layer (13') forming a molten alloy layer; vii) reciprocating, while maintaining the further temperature, the semiconductor chip (10') with respect to the conductive substrate (200) such that their surfaces are scrubbing each other. In the last step a solder layer is being formed comprising the molten alloy layer (13') and gold originating from the second attachment layer (14) consuming the second attachment layer (14). The reciprocating step is continued until the second attachment layer (14) is fully consumed. The method results in a further cost-down of the manufacturing method and semiconductor device.
摘要翻译：本发明涉及制造半导体器件（1'）的方法。该方法包括以下步骤：i）在其一侧提供包括硅层（11）的半导体芯片（10'），并且还包括直接在硅层（11）上的第一附着层（13），其中第一附着层（13）包括金; ii）将半导体芯片（10'）加热到高于预定温度，形成包含金 - 硅合金的合金层（13'）; iii）在合金层（13'）上直接提供第二附着层（14），其中第二附着层（14）包括金; iv）提供用于接收所述半导体芯片（10'）的导电衬底（200）; v）在导电衬底（200）的表面上提供半导体芯片（10'）; vi）将组件加热到形成熔融合金层的合金层（13'）的熔点之上的另外的预定温度; vii）相对于导电基板（200）使半导体芯片（10'）相互擦洗，同时保持进一步的温度往复运动。在最后步骤中，正在形成包含熔融合金层（13'）和消耗第二附着层（14）的来自第二附接层（14）的金的焊料层。往复运动的步骤继续进行，直到第二附着层（14）被完全消耗。该方法导致制造方法和半导体器件进一步降低成本。

3. 发明公开

EP2061072A2 Flip chip wafer, flip chip die and manufacturing processes thereof 审中-公开
标题翻译： Flipchip-Wafer，Flipchip和Herstellungsverfahren
公开(公告)号：EP2061072A2
公开(公告)日：2009-05-20
申请号：EP08167131.5
申请日：2008-10-21
申请人： BIOTRONIK CRM Patent AG
发明人： Chen, Singjang
IPC分类号： H01L21/60
CPC分类号： H01L24/94 , H01L21/563 , H01L23/293 , H01L23/3171 , H01L23/3192 , H01L24/11 , H01L24/27 , H01L24/73 , H01L2224/0401 , H01L2224/05572 , H01L2224/1132 , H01L2224/1146 , H01L2224/1147 , H01L2224/1148 , H01L2224/1162 , H01L2224/11849 , H01L2224/11901 , H01L2224/13022 , H01L2224/131 , H01L2224/16 , H01L2224/274 , H01L2224/27515 , H01L2224/27901 , H01L2224/29011 , H01L2224/29082 , H01L2224/29187 , H01L2224/73104 , H01L2224/73203 , H01L2224/94 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2924/0665 , H01L2924/01014 , H01L2224/29099 , H01L2924/00 , H01L2224/05552
摘要： The invention relates to a flip chip wafer comprising an active surface having a plurality of bumps (40, 41, 42) formed thereon and having at least one layer of a cured underfill material (30, 35, 36) accommodated between said plurality of bumps (40, 41, 42). The invention further comprises a flip chip die as well as processes for manufacturing a flip chip wafer and a flip chip die.
摘要翻译：本发明涉及一种倒装芯片晶片，其包括具有形成在其上的多个凸块（40,41,42）的活性表面，并且具有容纳在所述多个凸起之间的至少一层固化的底部填充材料（30,35,36）（40,41,42）。本发明还包括倒装芯片芯片以及用于制造倒装芯片晶片和倒装芯片裸片的工艺。

4. 发明公开

EP2061072A3 Flip chip wafer, flip chip die and manufacturing processes thereof 审中-公开
标题翻译：倒装芯片的晶片，和倒装芯片的制造方法
公开(公告)号：EP2061072A3
公开(公告)日：2012-07-11
申请号：EP08167131.5
申请日：2008-10-21
申请人： Biotronik CRM Patent AG
发明人： Chen, Singjang
IPC分类号： H01L21/60
CPC分类号： H01L24/94 , H01L21/563 , H01L23/293 , H01L23/3171 , H01L23/3192 , H01L24/11 , H01L24/27 , H01L24/73 , H01L2224/0401 , H01L2224/05572 , H01L2224/1132 , H01L2224/1146 , H01L2224/1147 , H01L2224/1148 , H01L2224/1162 , H01L2224/11849 , H01L2224/11901 , H01L2224/13022 , H01L2224/131 , H01L2224/16 , H01L2224/274 , H01L2224/27515 , H01L2224/27901 , H01L2224/29011 , H01L2224/29082 , H01L2224/29187 , H01L2224/73104 , H01L2224/73203 , H01L2224/94 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2924/0665 , H01L2924/01014 , H01L2224/29099 , H01L2924/00 , H01L2224/05552
摘要： The invention relates to a flip chip wafer comprising an active surface having a plurality of bumps (40, 41, 42) formed thereon and having at least one layer of a cured underfill material (30, 35, 36) accommodated between said plurality of bumps (40, 41, 42). The invention further comprises a flip chip die as well as processes for manufacturing a flip chip wafer and a flip chip die.

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