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1. 发明授权

EP2466587B1 Semiconductor storage device 有权
公开(公告)号：EP2466587B1
公开(公告)日：2020-09-02
申请号：EP11194028.4
申请日：2011-12-16
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Nagatsuka, Shuhei , Takahashi, Yasuyuki
IPC分类号： G11C16/02 , G11C11/403 , G11C11/404

2. 发明公开

EP2466587A3 Semiconductor storage device 审中-公开
标题翻译：半导体存储装置
公开(公告)号：EP2466587A3
公开(公告)日：2013-06-12
申请号：EP11194028.4
申请日：2011-12-16
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Nagatsuka, Shuhei , Takahashi, Yasuyuki
IPC分类号： G11C16/02 , G11C11/403 , G11C11/404
摘要： A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.

3. 发明公开

EP2428959A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：EP2428959A1
公开(公告)日：2012-03-14
申请号：EP11180109.8
申请日：2011-09-06
申请人： Semiconductor Energy Laboratory Co, Ltd.
发明人： Matsuzaki, Takanori , Nagatsuka, Shuhei , Inoue, Hiroki
IPC分类号： G11C8/08 , G11C11/403 , G11C11/405 , G11C11/408 , G11C16/02
CPC分类号： H01L27/1052 , G11C8/08 , G11C11/403 , G11C11/405 , G11C11/4085 , G11C16/02 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C2211/4016
摘要： A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.
摘要翻译：提供一种半导体器件，其中即使没有供电也可以保持存储的数据，并且不限制写入操作的次数。使用能够充分降低作为宽带隙半导体的氧化物半导体材料等晶体管的截止电流的材料来形成半导体装置。当使用能够充分降低晶体管的截止状态电流的半导体材料时，半导体器件可以长时间保存数据。另外，通过提供电连接到写入字线的电容器或噪声去除电路，可以减少或去除输入到存储器单元的诸如短脉冲或噪声的信号。因此，可以防止当存储器单元中的晶体管瞬时导通时写入存储器单元的数据被擦除的故障。

4. 发明公开

EP2405440A1 Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh 审中-公开
标题翻译：自动刷新自动刷新von Speicherzellen mit temperaturkompensiertem自刷新
公开(公告)号：EP2405440A1
公开(公告)日：2012-01-11
申请号：EP11007526.4
申请日：2007-03-30
申请人： MOSAID Technologies Incorporated
发明人： Pyeon, Hong Beom
IPC分类号： G11C11/406 , G11C11/403
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor. relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
摘要翻译：动态随机存取存储器（DRAM）器件具有逐列的DRAM单元阵列。阵列的每个DRAM单元与相应列的相应行和位线的字线耦合。通过模式检测器检测进入和退出自刷新模式，并提供自刷新模式信号。响应于自刷新模式信号产生的振荡电路产生基本时间段。第一分频器/时间周期乘法器根据与DRAM器件有关的过程变化因素来改变基本时间周期。第二分频器/时间周期乘法器根据温度变化因子进一步改变改变的时间段。涉及DRAM设备。在自刷新模式下，存储在DRAM单元中的数据被刷新。根据这两个因素，DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

5. 发明公开

EP2016588A4 DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION 审中-公开
标题翻译： DYNAMISCHER DIREKTZUGRIFFSSPEICHER MIT VOLLUNABHÄNGIGERPARTIALARRAY-AUFFRISCHFUNKTION
公开(公告)号：EP2016588A4
公开(公告)日：2009-08-05
申请号：EP07719431
申请日：2007-03-28
申请人： MOSAID TECHNOLOGIES INC
发明人： KIM JIN-KI , OH HAKJUNE
IPC分类号： G11C11/406 , G11C8/12 , G11C11/403
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
摘要翻译：动态随机存取存储器装置包括多个存储器子块。每个子块具有多个连接多个数据存储单元的字线。部分阵列自刷新（PASR）配置设置是独立完成的。根据PASR设置，存储器子块被寻址以进行刷新。 PASR设置由内存控制器完成。可以选择任何种类的子块地址组合。因此，存储器子块被完全独立地刷新。用于数据保存的用户可选存储器阵列提供有效的存储器控制编程，特别是对于低功率移动应用。

6. 发明公开

EP2016588A1 DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION 审中-公开
标题翻译：动态随机存取存储器完全自主PARTIALARRAY刷新
公开(公告)号：EP2016588A1
公开(公告)日：2009-01-21
申请号：EP07719431.4
申请日：2007-03-28
申请人： Mosaid Technologies Incorporated
发明人： KIM, Jin-Ki , OH, HakJune
IPC分类号： G11C11/406 , G11C11/403 , G11C8/12
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

7. 发明公开

EP1623432A4 SEMICONDUCTOR MEMORY CELL, ARRAY, ARCHITECTURE AND DEVICE, AND METHOD OF OPERATING SAME 审中-公开
标题翻译：半导体存储单元阵列，建筑以及设备和操作方法THEREFOR的
公开(公告)号：EP1623432A4
公开(公告)日：2007-02-21
申请号：EP04751661
申请日：2004-05-07
申请人： INNOVATIVE SILICON INC , ECOLE POLYTECH
发明人： FERRANT RICHARD , OKHONIN SERGUEI , CARMAN ERIC , BRON MICHEL
IPC分类号： G11C7/06 , G11C11/403 , G11C11/404 , G11C16/04 , G11C16/28 , H01L20060101 , H01L27/108
CPC分类号： G11C16/28 , G11C11/404 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell (FIG. 3A, 3B) includes two transistors (102a, 102b) which store complementary data states (“0”, “1”). That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary '0') and the other transistor of the memory cell stores a logic high (a binary “l”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell (FIG. 4). That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

8. 发明公开

EP1329896A4 SEMICONDUCTOR MEMORY AND CONTROL METHOD 审中-公开
标题翻译：半导体存储器控制方法
公开(公告)号：EP1329896A4
公开(公告)日：2006-01-25
申请号：EP01984292
申请日：2001-07-26
申请人： NEC ELECTRONICS CORP
发明人： TAKAHASHI HIROYUKI , SONODA MASATOSHI
IPC分类号： G11C11/403 , G11C8/18 , G11C11/406 , G11C11/408 , G11C11/401
CPC分类号： G11C11/40615 , G11C8/18 , G11C11/406 , G11C11/408
摘要： A semiconductor memory in which no operating current caused by the noise of an address signal fed from outside is effectively suppressed without retarding the operating speed during read/write. The semiconductor memory comprises a circuit system including a filter circuit (102) for removing the noise of an address signal fed from outside and an ATD circuit (311) for detecting a transition of the address signal before it passes through the filter circuit (102) and generating a first address transition detection signal ( ζATD1) if a transition is detected and a circuit system including an ATD circuit (321) for detecting a transition of the address signal after it passes the filter circuit (102) and generating a second address transition detection signal ( ζATD2) if a transition is detected. The refresh is controlled by the first address transition detection signal ( ζATD1), and the read/write is controlled by the second address transition detection signal (ζATD2). Thus if noise is generated, only refresh is carried out, and the operating current is effectively suppressed. A method for controlling such a semiconductor memory is also disclosed.

9. 发明授权

EP1540658B1 REFRESHING OF MULTI-PORT MEMORY IN INTEGRATED CIRCUITS 有权
标题翻译：在一体化电路中刷新多端口存储器
公开(公告)号：EP1540658B1
公开(公告)日：2005-12-28
申请号：EP03797250.2
申请日：2003-08-26
申请人： Infineon Technologies AG
发明人： JAIN, Raj Kumar
IPC分类号： G11C11/406 , G11C11/403 , G11C7/10 , G11C8/16
CPC分类号： G11C11/40603 , G11C11/403 , G11C11/405 , G11C11/406
摘要： A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh operation is described. The refresh operation is allocated to the port that is not externally accessed. When accesses through both ports are requested, a wait cycle for one of the access requests is inserted until the refresh is terminated.
摘要翻译：描述了包括用于刷新以便检测外部请求的访问和刷新操作之间的冲突的竞争电路的双端口存储器模块。刷新操作分配给未从外部访问的端口。当请求通过两个端口的访问时，将插入一个访问请求的等待周期，直到刷新结束。

10. 发明公开

EP1405314A2 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：EP1405314A2
公开(公告)日：2004-04-07
申请号：EP02745383.6
申请日：2002-06-05
申请人： Innovative Silicon SA , Ecole Polytechnique Fédérale de Lausanne (EPFL)
发明人： FAZAN, Pierre, Christophe , OKHONIN, Serguei
IPC分类号： G11C11/404 , G11C11/403 , H01L27/108
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.
摘要翻译：公开了一种半导体器件，例如存储器件或辐射检测器，其中数据存储单元形成在衬底13上。每个数据存储单元包括具有源极18，漏极22和栅极28的场效应晶体管，以及布置在源极和漏极之间用于存储体内产生的电荷的主体。可以通过施加到晶体管的输入信号来调节主体22中的净电荷的大小，并且可以通过在栅极28与栅极28之间施加电压信号来至少部分地抵消输入信号对净电荷的调节漏极22以及源极18和漏极22之间。

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